AnsweredAssumed Answered

STM324x9I-EVAL1 and SDRAM timings

Question asked by gonzalez.laurent on Apr 22, 2014
Hi there,

I've been surprised to hit BW limit of SDRAM on the eval board. This happened trying to transfer DCMI data to SDRAM, while using SDRAM as data segment as well.

Entering the gory details, I checked setup/timings of system_stm32f4xx.c, from Standard STLib and STM32cube as well, both seems to be sub-optimal to me. Access is 16bit, SDCR init setup CL3 and SDRAM mode register configures no burst.

STM324x9I-EVAL1 has ISSI 48S32800G-6BLI 2M*32bit*4bank SDRAM rated for 166MHZ@CL3 and 100MHZ@CL2. HCLK being 180MHZ, SDRAM CLK is 90MHZ, so CL2 should be possible.

I tried to optimize by setting 0x00001960 in SDCR, and 0x00004014 in SDCMR for mode register load. For the time being I only focused on timing, I am pretty sure I have the wrong number of row/col ... I am not comfortable with that wizardry and even if first test are successful I am afraid those values being too aggressive and likely to produce unstable systems.

Well, my question is coming: does anyone has ever tried to calculate optimal timings, and be nice enough to share with us ?

Outcomes