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[bug report] SPDIFRX divider error

Question asked by tutak.mikolaj on Oct 14, 2016
Latest reply on Jan 6, 2017 by Sirma Siang
Hi All,

I've discovered that code generated with STM32 CubeMX for SPDIFRX is faulty. SPDIFRX has dedicated PLL divider which has 2 bits (0=1/2, 1=1/4, 2=1/6 or 3=1/8), however code generates uses 4 defines which have 2, 4, 6 and 8 values. Those values are truncated to 2 bits which makes that you can select only 2 dividers:

selected 1/2 (2) becomes 1/6 (2)
selected 1/4 (4) becomes 1/2 (0)
selected 1/6 (6) becomes 1/6 (2)
selected 1/8 (8) becomes 1/2 (0)


This is a $%^%$# frustrating because hou have to correct this after EACH code generations. I've checked this on F746 and F767 with same results!

regards
Mikołaj Tutak

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