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DMA FIFO Flush Issue

Question asked by zarovy.s on Feb 20, 2014
Latest reply on Jun 16, 2015 by elliott.grant

I am using a STM32F4 as a SPI slave. The STM32F4 receives a packet of data over a USART line and must have the data immediately available for use in the SPI communication. I am using a DMA Tx memory to peripheral transfer on the SPI line to quickly shift out data. In order to make the fresh data immediately available to the SPI DMA I am attempting to flush the DMA FIFO buffer to remove the data that was automatically loaded into the buffer after the previous SPI transfer. I  reset the EN bit of the DMA register to start the FIFO flush and a little bit later the DMA TCIF bit is set which I think is suppose to signify the flush is complete. However after enabling the DMA again, in the next SPI transfer, the data is incorrect. The first byte sent is the last byte from the previous SPI transfer, the second byte is the first byte of the new data packet, and the third byte is the second byte of the new data packet and so on. I am thinking I am simply not flushing the FIFO buffer and re-enabling the DMA stream properly. I have checked the remaining data counter, DMA_SxNDTR and  it shows full number of bytes after a flush. I am not sending too big of a data packet (only 96 bits) but I am stuck in the structure of needing to act as a SPI slave and receive fresh data in real time.  Any tips or suggestions would be greatly appreciated.