AnsweredAssumed Answered

I2S clock frequency problem

Question asked by khan.zarar on Feb 7, 2014
Latest reply on Nov 4, 2015 by em3ly
Hi,

I am interfacing TLV320AIC3204 to stm32f415, at this stage i am able to configure codec IC using I2C successfully and also able to operate I2S interface in full duplex mode with DMA on both transmission and reception, problem i am having is with generating correct sampling frequency. I am trying to set Fs = 48KHz. 

Controller is operating on HSE=8MHz with controller PLL enabled and also I2SPLL with PLL_M = 8 ; PLL_N = 336 ; PLL_P = 2 ; PLL_Q = 7 ; PLLI2S_N = 258; PLLI2S_R = 3;

i have verified controller is indeed operating at 168MHz and also all the PLL dividers and multipliers are set of the correct value which i set using the system file. which makes I2SCLK = 86MHz. 


Everything is fine till this point but according to specifications which i mentioned in system_stm32f4xx.c I2SDIV = 3 and ODD =1; but when i check in the debugger for these bits i see I2SDIV to be set to '11' and ODD = 0; using these values if i calculate Fs theoretically i get 15.269KHz and that is the same frequency which i get practically (i verified using MCLK pin which is 256*Fs). 

Can anyone kindly mention any CMSIS API to manually set ODD=1 and I2SDIV =3, (or any other method), any help would be highly appreciated. Waiting for ur kind response.

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