AnsweredAssumed Answered

I2S MCLK slew rate issue

Question asked by Reay.Donald on Jan 22, 2014
Latest reply on Jan 23, 2014 by Reay.Donald

I've been using an audio codec with the STM32F407 Discovery. Data is transferred using I2S, with the STM32F407 as master.
It generates an MCLK signal at a frequency of 256*fs, i.e at 2.048 MHz for 8 kHz sampling rate and 12.288 MHz for 48 MHz
sampling rate.
So far so good.
But when I tried the same thing on an STM32F401 Discovery (with a processor clock rate of 84 MHz) 48 kHZ sampling wouldn't
I think this is due to the nature of the MCLK signal. Its slew rate is limited and while at 2.048 MHz MCLK appears roughly
square, at 12.288 MHz it appears triangular. In the case of the 168 MHz F407, it rises to around 3 volts in half a period,
in the case of the 84 MHz F401 it rises only to around 2 volts and I think that the codec is not recognising this as a
clock signal.
Is there any way of getting a faster rise time on MCLK?

Here's a very small code snippet -

  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;

  GPIO_InitStructure.GPIO_Pin = I2Sx_CK_PIN;
  GPIO_Init(I2Sx_CK_GPIO_PORT, &GPIO_InitStructure);

I've tried different GPIO_Speed settings but they don't appear to have any effect.

Physically disconnecting the MCLK pin (PC6) from the codec and looking at the un-loaded output signal it looks the same.

Thanks for any advice!