AnsweredAssumed Answered

Speed of STM32F10vct6 FSMC interfacing with TFT LCD

Question asked by sruthi on Aug 8, 2016
Latest reply on Aug 8, 2016 by Clive One

Hi, I am working with SSD1963 7"TFT(800x480) with stm32f10vct6 controller. Right now refresh rate that I am able to achieve is 5 FPS. Is that the maximum speed? May I get much more speed with the same controller?  please take a look FSMC INIT code and SSD1963 init code that I’m using are given below.

FSMC Init

void LCD_FSMCConfig(void)

{

  FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;

  FSMC_NORSRAMTimingInitTypeDef  p;

/*-- FSMC Configuration ------------------------------------------------------*/

  /* FSMC_Bank1_NORSRAM4 timing configuration */

  p.FSMC_AddressSetupTime = 0;

  p.FSMC_AddressHoldTime = 0;

  p.FSMC_DataSetupTime = 1;

  p.FSMC_BusTurnAroundDuration = 0;

  p.FSMC_CLKDivision = 1;

  p.FSMC_DataLatency = 0;

  p.FSMC_AccessMode = FSMC_AccessMode_B;

  /* FSMC_Bank1_NORSRAM4 configured as follows:

        - Data/Address MUX = Disable

        - Memory Type = SRAM

        - Data Width = 16bit

        - Write Operation = Enable

        - Extended Mode = Disable

        - Asynchronous Wait = Disable */

  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;

  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;

  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;

  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;

  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;

  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;

  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;

  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;

  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;

  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;

  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;

  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;

  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;

  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;

  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 

  /* Enable FSMC_Bank1_NORSRAM4 */

  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);

}

/**

  * @brief  Initializes the FSMC NOR/SRAM Banks according to the

  *   specified parameters in the FSMC_NORSRAMInitStruct.

  * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef

  *   structure that contains the configuration information for

  *   the FSMC NOR/SRAM specified Banks.                      

  * @retval : None

  */

void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)

{

  /* Check the parameters */

  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));

  assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));

  assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));

  assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));

  assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));

  assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));

  assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));

  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));

  assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));

  assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));

  assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));

  assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); 

  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));

  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));

  assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));

  assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));

  assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));

  assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));

  assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));

 

  /* Bank1 NOR/SRAM control register configuration */

  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =

            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |

            FSMC_NORSRAMInitStruct->FSMC_MemoryType |

            FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |

            FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |

            FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |

            FSMC_NORSRAMInitStruct->FSMC_WrapMode |

            FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |

            FSMC_NORSRAMInitStruct->FSMC_WriteOperation |

            FSMC_NORSRAMInitStruct->FSMC_WaitSignal |

            FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |

            FSMC_NORSRAMInitStruct->FSMC_WriteBurst;

  if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)

  {

    FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;

  }

  /* Bank1 NOR/SRAM timing register configuration */

  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =

            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |

            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |

            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |

            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |

            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |

            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |

             FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;

           

   

  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */

  if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)

  {

    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));

    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));

    assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));

    assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));

    assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));

    assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));

    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =

              (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |

              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|

              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |

              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |

              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |

               FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;

  }

  else

  {

    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;

  }

}

/**

  * @brief  Enables or disables the specified NOR/SRAM Memory Bank.

  * @param FSMC_Bank: specifies the FSMC Bank to be used

  *   This parameter can be one of the following values:

  * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 

  * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2

  * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3

  * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4

  * @param NewState: new state of the FSMC_Bank.

  *   This parameter can be: ENABLE or DISABLE.

  * @retval : None

  */

void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)

{

  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));

  assert_param(IS_FUNCTIONAL_STATE(NewState));

 

  if (NewState != DISABLE)

  {

    /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */

    FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;

  }

  else

  {

    /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */

    FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;

  }

}

SSD1963 Init

void SSD1963_Initial(void)

                vWrite_command(0x00E2);         //PLL multiplier, set PLL clock to 120M

                vWrite_Data_int(0x0022);                //N=0x36 for 6.5M, 0x23 for 10M crystal

                vWrite_Data_int(0x0003);

                vWrite_Data_int(0x0054);

                vWrite_command(0x00E0);  // PLL enable

                vWrite_Data_int(0x0001);

                delayus(10);

                vWrite_command(0x00E0);

                vWrite_Data_int(0x0003);                            // now, use PLL output as system clock

                delayus(10);

                vWrite_command(0x0001);  // software reset

                delayus(20);

                vWrite_command(0x00E6);         //PLL setting for PCLK, depends on resolution

                vWrite_Data_int(0x0003);

                vWrite_Data_int(0x0033);

                vWrite_Data_int(0x0033);

                vWrite_command(0x00B0);        //LCD SPECIFICATION

                vWrite_Data_int(0x0020); //24 bit TFT panel

               

//            vWrite_Data_int(0x0080);

//            vWrite_Data_int(0x0003);

//            vWrite_Data_int(0x001F);

//            vWrite_Data_int(0x0001);

//            vWrite_Data_int(0x00DF);

//            vWrite_Data_int(0x0000);

               

                vWrite_Data_int(0x0000); //Hsync+Vsync +DE mode  TFT mode

                vWrite_Data_int((799>>8));  //Set HDP

                vWrite_Data_int(31);

    vWrite_Data_int(479>>8);  //Set VDP

                vWrite_Data_int(223);

    vWrite_Data_int(0x0000);

                vWrite_command(0x00B4);        //HSYNC

                vWrite_Data_int(0x04);  //Set HT

                vWrite_Data_int(0x20);

                vWrite_Data_int(0x00);

                vWrite_Data_int(0x2E);

                vWrite_Data_int(0xD2);

               

//            vWrite_Data_int(0x1f);

//            vWrite_Data_int(0x00);  //Set HPS

//            vWrite_Data_int(0xd2);

//            vWrite_Data_int(0x00);                                                   //Set HPW

                vWrite_Data_int(0x00);  //Set HPS

                vWrite_Data_int(0x00);

                vWrite_Data_int(0x00);

                vWrite_command(0x00B6);        //VSYNC

                vWrite_Data_int(0x02);   //Set VT

                vWrite_Data_int(0x0D);

                vWrite_Data_int(0x00);

                vWrite_Data_int(0x17);

                vWrite_Data_int(0x16);

               

               

//            vWrite_Data_int(0x0c);

//            vWrite_Data_int(0x00);  //Set VPS

//            vWrite_Data_int(0x22);

//            vWrite_Data_int(0x00);                                //Set VPW

                vWrite_Data_int(0x00);  //Set FPS

                vWrite_Data_int(0x00);

                /*************************************/

                                vWrite_command(0x002A);       

                vWrite_Data_int(0x00);

                vWrite_Data_int(0x00);

                vWrite_Data_int(0x01);

                vWrite_Data_int(0xDF);

                                vWrite_command(0x002B);       

                vWrite_Data_int(0x00);

                vWrite_Data_int(0x00);

                vWrite_Data_int(0x03);

                vWrite_Data_int(0x1F);
}

                /**************************/

Outcomes