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The use of spi clock phase

Question asked by wu.leon on Nov 13, 2013
I'm trying to use spi  to talk to a EEPROM. It has a cs setup time of 200ns. I'm wondering if  I can set the CPHA to meet the requirement in case the spi speed is in the proper range. Is this the purpose of clock phase? Of course the 100ns setup time can be met by use some delay before write data to spi. If the answer to the previous question is yes, which way is better in practice. The delay may be not optimal but more robust in case we accelerate the spi speed afterwards.
 Additionally if CPOL is 0, how the clock will look like just after  lowing NSS. will it stay low for half period than rise or there is no guarantee?