I’m starting to deal with STM32F30 discovery.
I need confirmation about my assertion on default clock configuration for the stm32f3discovery_fw.
In file system_stm32f30x.c the define PLL_SOURCE_HSE_BYPASS is uncommented
// HSE bypassed with an external clock (8MHz, coming from ST-Link) used to clock the PLL, and the PLL is used as system clock source
In this case the function SystemInit() calls the functions SetSysClock():
#elif defined (PLL_SOURCE_HSE_BYPASS)
/* HSE oscillator bypassed with external clock */
RCC->CR |= (uint32_t)(RCC_CR_HSEON | RCC_CR_HSEBYP);
The same function sets HCLK = SYSCLK = PCLK2 = PCLK1 and PLLCLK = HSE * 9 = 72 Mhz and then Select PLL as system clock source, this meanse that HCLK = 72 Mhz
SysTick_Config() configure the SysTick Counter clock source to be Core Clock Source (HCLK).
At the end I understood that SysTick Counter clock is 72 Mhz.
This means that SysTick_Config(SystemCoreClock / 1000) give an interrupts every 72000 clock cycle, that is an interrupt every 0.1 ms , is it correct?
Your support is very appreciate.