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Bug in stm32f4xx_hal_rcc.c/version V1.4.3

Question asked by khazhakyan.ruben on Jan 30, 2016
Latest reply on Feb 1, 2016 by Amel N
See line 678 :

The intend is to  check System clock switch status (SWS field of RCC_CFGR)  after writing to System clock switch (SW field of RCC_CFGR). But the definition of RCC_SYSCLKSOURCE_STATUS_PLLRCLK is wrong. As a result that statement never gets false which leads to timeout. In turn, that leads to skipping initialization of PPRE1 and PPRE2 of RCC_CFGR. The consequence  is:  APB1 and APB2  clocks are the same as AHB clock when AHB prescaler = 1.  So, if SYSCLK is 180 MHz the APB1 will run at the same clock (should be 45 MHz max) ! Wow!
Conclusion: The definition of  RCC_SYSCLKSOURCE_STATUS_PLLRCLK should point to bits 3:2 instead of 1:0 of RCC_CFGR register