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STR752 RTC problem

Question asked by philipd on Aug 5, 2010

Hi

I am having trouble getting my RTC to run of the CK_OSC4M / 128. Up to now I have been using 32 khz crystal oscillator but now need to use the internal clock at board space is an issue. Can anybody help as I can not see anything wrong with what I am doing.

CKRTCBYP_BIT  = 0x40000000 // RTC oscillator bypass
CKRTCSEL_BIT  = 0x01000000 // RTC Clock Select .. bit 25 = 0 bit 24 = 1
CKRTCSEL_MASK  = 0xFCFFFFFF 

Code  

Reset_Handler:      // after a reset start here
 ldr r0,=CFG_GLCONF_Addr
 ldr r1,[r0]
 orr r1,r1,#FLASH_BURST_BIT
 str r1,[r0]

// --------------------------------------------------------------------------
// Description  :  Start the clocks and switch to the PLL
// --------------------------------------------------------------------------
 ldr r0,=MRCC_BASE_Addr   // MCU Reset and Clock Control
 ldr r1,=MRCC_CLKCTL_Val
 ldr r2,[r0,#MRCC_CLKCTL_OFS]
 ldr r5,=DIV_MASK
 mvn r6,r5
 and r5,r1,r5
 and r6,r2,r6
 orr r5,r5,r6
 str r5,[r0,#MRCC_CLKCTL_OFS]

 ldr r2,[r0,#MRCC_CLKCTL_OFS] // wait presence of osc clk
 bic r2,r2,#NCKDF_BIT
wait_osc_pres:
 str r2,[r0,#MRCC_CLKCTL_OFS] // write 0 to NCKDF Flag
 ldr r1,[r0,#MRCC_CLKCTL_OFS] // read       NCKDF Flag
 ands r1,r1,#NCKDF_BIT
 bne wait_osc_pres    // if NCKDF Flag set to 1

wait_clk_stable:
 ldr r1,[r0,#MRCC_RFSR_OFS]  // wait stable clock
 ands r1,r1,#BCOUNTF_BIT
 beq wait_clk_stable

 ldr r1,[r0,#MRCC_CLKCTL_OFS] // switch CK_SYS to CK_OSC4M
 orr r2,r1,#CKSEL_BIT
 str r2,[r0,#MRCC_CLKCTL_OFS]

 ldr r1,=MRCC_CLKCTL_Val   // setup PLL multiply factor .. note PLL is by default disabled
 ldr r2,[r0, #MRCC_CLKCTL_OFS] // load current CLKCTL value
 ldr r3,=MUL_MASK
 mvn r4,r3
 and r3,r1,r3
 and r4,r2,r4
 orr r3,r3,r4
 str r3,[r0,#MRCC_CLKCTL_OFS] // load multiply value

 ldr r1,[r0,#MRCC_CLKCTL_OFS] // enable the PLL
 orr r1,r1,#PLL_EN_BIT
 str r1,[r0,#MRCC_CLKCTL_OFS]

PLL_locking:
 ldr r1,[r0,#MRCC_CLKCTL_OFS] // wait for PLL to lock
 ands r1,r1,#PLL_LOCK_BIT
 beq PLL_locking

 ldr r1,[r0,#MRCC_CLKCTL_OFS] // switch CK_SYS to CK_PLL1
 bic r1,r1,#CKSEL_BIT
 str r1,[r0,#MRCC_CLKCTL_OFS]

// --------------------------------------------------------------------------
// Description  :  Start the RTC
// --------------------------------------------------------------------------
  ldr r1,[r0,#MRCC_PWRCTRL_OFS]
 and r1,r1,#CKRTCSEL_MASK
 orr r1,r1,#CKRTCSEL_BIT  
 str r1,[r0,#MRCC_PWRCTRL_OFS] // enable internal 4mhz / 128 .. RTC clock. 

// --------------------------------------------------------------------------
// Description  :  Initialize stack pointer registers
// --------------------------------------------------------------------------
 ldr r0,=End_of_RAM

 msr CPSR_c,#Mode_UNDEF|I_Bit|F_Bit // No interrupts
 mov sp,r0
 sub r0,r0,#UNDEF_Stack_Size

 msr CPSR_c,#Mode_ABT|I_Bit|F_Bit // No interrupts
 mov sp,r0
 sub r0,r0,#ABT_Stack_Size

 msr CPSR_c,#Mode_SVC|I_Bit|F_Bit // No interrupts
 mov sp,r0
 sub r0,r0,#SVC_Stack_Size

 msr CPSR_c,#Mode_FIQ|I_Bit|F_Bit // No interrupts
 mov sp,r0
 sub r0,r0,#FIQ_Stack_Size

 msr CPSR_c,#Mode_IRQ|I_Bit|F_Bit // No interrupts
 mov sp,r0
 sub r0,r0,#IRQ_Stack_Size

 msr CPSR_c,#Mode_SYS|I_Bit|F_Bit // No interrupts
 mov sp,r0

// **************************************************************************
// Now enter the C code
// Note : use B not BL, because an application will never return this way
// **************************************************************************
 b Main

 

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