I have a question regarding the maximum clock frequency for the ADC. The data sheet on STM32F407 gives maximum clock frequency for ADC as 36 MHz (Doc ID 022152, Rev 3, page 124) for power supply of 3.6 V.
However, there are examples at ST site that use higher clock frequency of 168/4 = 42 MHz. This is the case in the latest version of Standard Peripheral Library package ("stm32f4_dsp_stdperiph_lib.zip" obtained today from the ST site), but not the case in the "STM32F4-Discovery_FW_V1.1.0" package (where correct "system_stm32f4xx.c" file defining the ADC clock at 36 MHz is used).
Which of the two clock frequencies should I use: 36MHz or 42 MHz? I have tested the ADC using both clock frequencies and the shortest sampling time of 3 clock periods, but noticed no difference regarding the resolution or missing codes of the ADC.
The point here is that the requirement to use the 36 MHz clock for ADC reduces the clock frequency for the CPU from 168 to 144 MHz, and therefore slows down the execution of the program for about 15%. My application includes sampling at about 1 MHz and on-line filtering. Speed here is of importance.
Thanks and best regards