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NAND Flash support with larger page size and more addressing cycles

Question asked by Niclaes.Christophe on Oct 8, 2015
Latest reply on Oct 9, 2015 by Clive One
I've a new project were I need to use NAND flash connected to STM32F2 or STM32F4. I need to support NAND Flash chips with 8, 16, 32 or 64 Gbits. These chips have page size of 4096 or 8192 bytes, and the required number of Addressing Cycle is usually 5.

The current NAND Flash driver of STM32Cube's FW is only supporting 512 and 2048 bytes for the page size, and the maximum number of Addressing Cycle is 4.

When looking at STM32's reference manual:
- there is no limitation on the FMSC about the number of Addressing Cycles -> OK
- the ECC calculation can be done on 4096 or 8192 bytes -> OK

So my first questions are about the S/W support for this chips:
- Is it possible to adapt the NAND Flash driver for support of larger NAND Flashes?
- Is this code available from ST?

When the driver will be working, I would like to use FATFS with FAT32 mode.

It seems that FatFs support only block size (at FAT level) of maximum 4K. Does it mean that block size of 8K at NAND level won't be supported?

And the last question: on STEVAL-CCM07 board, ST was providing a complete firmware for NAND Flash management, wear leveling, ... Is this code available in Cube ? I can see FatFs, NAND Driver, but not the glue between them !