STM8S pwm capture does not work

[christian-at]

Hallo.
I want to measure a pwm-signal (period 20ms, Puls 1,5ms +- 0,5ms)
I made a assembler program to capture the positive and negative transitions of the signal according the RefManual RM0016, Rev14, page 170.
I tried various versions but the negative transition is never captured, TIM1_CCR2 contains the period value or 0. TIM1CCR1 contains the period value as expected.
where is my fault ?
Please support.
Sincerely
Christian

stm8/
;************************************************************************ 
; TITLE:		fsm1.asm
; AUTHOR:           SCh, 25 10 01 SCh
; Copyright 2015- , Dipl.-Ing.Christian Schmid, A-4973 St.Martin
; DESCRIPTION:	Funkschaltmodul
;
;         0.10, 24 07 24 SCh, erster Test ?
;	0.13, 25 11 11 SCh,
;	0.14, 25 11 12 SCh,
;************************************************************************

;Macros


;----------------------


	#include "mapping.inc"
	#include "STM8S105x.asm"	;<- verwendeter uC K4
	
;Konstante (bytes)
	BYTES
	
FREQ	EQU	2	;=fmaster=fosz/CLK_CKDIVR

NSER	EQU	8	;Anzahl bytes seriell aus

MU	EQU	162	;Schaltwert unten
MO	EQU	213	;Schaltwert oben
MM	EQU	187	;Wert Mitte


;Variable
	segment 'ram0'
	BYTES

v	DS.B	1	;Var zeiten
v1	DS.B	1	;


eing	DS.B	1	;Merker: 0:Eingang


	
	segment 'ram1'
	WORDS

buf	DS.B	8	;Buffer i2c


;---

	segment 'eeprom'
	WORDS
eeprom	DS.B	64

	
;Programm
	segment 'rom'
	WORDS

;Konstante (words)
FAK1	EQU	8700


;Texte            xxxxxxxxxxxxxxxx
	STRING "Version014  fsm1"		;

;Tabelle

		
start:
;initialize int. Oszillator
	mov CLK_CKDIVR,#%00011000     ;set internal clock 2MHz

;initialize SP
	ldw X,#stack_end
	ldw SP,X

	#ifdef RAM0	
;clear RAM0
ram0_start.b	EQU $ram0_segment_start
ram0_end.b	EQU $ram0_segment_end
	ldw X,#ram0_start
clear_ram0
	clr (X)
	incw X
	cpw X,#ram0_end	
	jrule clear_ram0
	#endif

	#ifdef RAM1
;clear RAM1
ram1_start.w	EQU $ram1_segment_start
ram1_end.w	EQU $ram1_segment_end	
	ldw X,#ram1_start
clear_ram1
	clr (X)
	incw X
	cpw X,#ram1_end	
	jrule clear_ram1
	#endif

;clear stack
stack_start.w 	EQU $stack_segment_start
stack_end.w	EQU $stack_segment_end
	ldw X,#stack_start
clear_stack
	clr (X)
	incw X
	cpw X,#stack_end	
	jrule clear_stack

;STM8S105C6T6 48pin LQFP48 (Pin v=vorhanden, nc=nicht vorhanden)
;config io: dd:0=in,1=out, cr1:0=fl/od,1=wpu/pp, cr2:0=noint/slow,1=int/fast
;Port A
	mov PA_ODR,#%00000000	;0:nc		1v:Oszin
	mov PA_DDR,#%01101000	;2v:Oszout	3v:pp
	mov PA_CR1,#%01111110	;4v:in pu		5v:pp
	mov PA_CR2,#%00000000	;6v:pp		7:nc
;Port B
	mov PB_ODR,#%00110000	;0v:frei		1v:frei
	mov PB_DDR,#%00010000	;2v:frei		3v:frei
	mov PB_CR1,#%11001111	;4v:SCL od	5v:SDA in fl
	mov PB_CR2,#%00000000	;6v:frei		7v:frei
;Port C
	mov PC_ODR,#%00000000	;0:nc		1v:TIM1ch1 in fl
	mov PC_DDR,#%00000000	;2v:TIM1ch2 infl ?	3v:frei
	mov PC_CR1,#%11111000	;4v:frei		5v:frei
	mov PC_CR2,#%00000000	;6v:frei		7v:frei
;Port D
	mov PD_ODR,#%00000000	;0v:pp LED	1v:SWIM, in fl
	mov PD_DDR,#%00100001	;2v:frei		3v:frei
	mov PD_CR1,#%10111101	;4v:frei		5v:TX pp
	mov PD_CR2,#%00000000	;6v:RX,in fl	7v:frei
;Port E
	mov PE_ODR,#%00000000	;0v:frei		1v:frei
	mov PE_DDR,#%00000000	;2v:frei		3v:frei
	mov PE_CR1,#%01101001	;4:nc		5v:frei
	mov PE_CR2,#%00000000	;6v:frei		7v:frei
;Port F
	mov PF_ODR,#%00000000	;0:nc		1:nc
	mov PF_DDR,#%00000000	;2:nc		3:nc
	mov PF_CR1,#%00000000	;4:nc		5:nc
	mov PF_CR2,#%00000000	;6:nc		7:nc
;Port G
	mov PG_ODR,#%00000000	;0v:frei		1v:frei
	mov PG_DDR,#%00000000	;2:nc		3:nc
	mov PG_CR1,#%00000011	;4:nc		5:nc
	mov PG_CR2,#%00000000	;6:nc		7:nc

;TIM1
	mov TIM1_PSCRH,#%00000000	;
	mov TIM1_PSCRL,#%00001111	; :16(4)=8usec pro Stufe
	mov TIM1_CCMR1,#%00000001	;ch 1, Periode
	mov TIM2_CCER1,#%00100000	;4:en ch2, 0:en ch1
	mov TIM1_CCMR2,#%00000010	;ch 2, Duty	
	mov TIM2_CCER2,#%00000000	;4:en ch4, 0:en ch3	
	mov TIM1_CCMR3,#%00000000	;ch 3,
	mov TIM1_CCMR4,#%00000000	;ch 4,	
	mov TIM1_SMCR,#%01010100	;source	
;	mov TIM1_EGR,#%00000110	;Ereignis
	mov TIM1_IER,#%00000110	;Interrupt enable	

;	bset TIM1_CR1,#0		;enable counter TIM1

;TIM2
	
;SPI

;ADC

;UART seriell
;	mov UART2_BRR2,#$01		;
;	mov UART2_BRR1,#$1a		;19200 Bd f r 8Mhz
	mov UART2_BRR2,#$08		;
	mov UART2_BRR1,#$06		;19200 Bd f r 2MHz

	mov UART2_CR2,#%00001000	;tx enable
	

;usermain                   

	clr eing
	mov {buf+0},#0
	mov {buf+1},#0
	mov {buf+2},#0
	mov {buf+3},#0	
	mov {buf+4},#0		;TEST
	mov {buf+5},#%11100111	;TEST E7
	mov {buf+6},#0	
	mov {buf+7},#0
	
	
	bset TIM1_CCER1,#0		;enable capture 1
	bset TIM1_CCER1,#4		;enable capture 2
	bset TIM1_CR1,#0		;enable counter TIM1
	clr TIM1_SR1	
	clr TIM1_SR2
	
	rim			;enable all interrupts
	

; main program loop


schleife:
	call t20
	call t20
	call t20	
	ld A,{buf+3}
	cp A,#MO
	jrnc hp_2			;>=
	cp A,#MU
	jrc hp_3			;<
	bres PA_ODR,#5
	bres PA_ODR,#6
	jp hp_9
hp_2	bset PA_ODR,#6
	bres PA_ODR,#5
	jp hp_9
hp_3	bres PA_ODR,#6
	bset PA_ODR,#5
hp_9	bcpl PD_ODR,#0		;Led blinkt
	call ser_out
	jp schleife		;5ms+serout
	


;UP	

ser_out:
	clrw X
wait_txe	btjf UART2_SR,#7,wait_txe	;warte bis TXE=1
	ld A,(buf,X)
	ld UART2_DR,A
	incw X
	cpw X,#NSER
	jrne wait_txe
	ret


t20	mov v,#{14 mult FREQ}		;20ms
zeit1	mov v1,#236
zeit2	nop
	nop
	nop
	dec v1
	jrne zeit2
	dec v
	jrne zeit1
	ret
	

;-----------------------------

;externe SUB



;Interrupt Handler
	interrupt NonHandledInterrupt
NonHandledInterrupt
	iret
	
	interrupt tim1cap
tim1cap
	ld A,TIM1_SR1
	ld {buf+4},A	
	and A,#%00000010
	jreq tm1c_14	;nur lesen wenn capture2
	mov {buf+0},TIM1_CCR1H
	mov {buf+1},TIM1_CCR1L	;lese Periode
	bcpl PA_ODR,#3		;Ausgang blinkt
tm1c_14	ld A,{buf+4}
	and A,#%00000100
	jreq tm1c_15
	mov {buf+2},TIM1_CCR2H
	mov {buf+3},TIM1_CCR2L	;lese Duty
	clr TIM1_SR1	
	jp tm1c_19	
tm1c_15	clr TIM1_SR1	;;
tm1c_19	mov {buf+6},TIM1_SR2	
	clr TIM1_SR2	
	iret	

	segment 'vectit'
	dc.l {$82000000+start}		; reset
	dc.l {$82000000+NonHandledInterrupt}	; trap
	dc.l {$82000000+NonHandledInterrupt}	; irq0
	dc.l {$82000000+NonHandledInterrupt}	; irq1
	dc.l {$82000000+NonHandledInterrupt}	; irq2
	dc.l {$82000000+NonHandledInterrupt}	; irq3
	dc.l {$82000000+NonHandledInterrupt}	; irq4
	dc.l {$82000000+NonHandledInterrupt}	; irq5
	dc.l {$82000000+NonHandledInterrupt}	; irq6
	dc.l {$82000000+NonHandledInterrupt}	; irq7
	dc.l {$82000000+NonHandledInterrupt}	; irq8
	dc.l {$82000000+NonHandledInterrupt}	; irq9
	dc.l {$82000000+NonHandledInterrupt}	; irq10
	dc.l {$82000000+NonHandledInterrupt}	; irq11
	dc.l {$82000000+tim1cap}		; irq12 TIM1 CC
	dc.l {$82000000+NonHandledInterrupt}	; irq13
	dc.l {$82000000+NonHandledInterrupt}	; irq14
	dc.l {$82000000+NonHandledInterrupt}	; irq15
	dc.l {$82000000+NonHandledInterrupt}	; irq16
	dc.l {$82000000+NonHandledInterrupt}	; irq17
	dc.l {$82000000+NonHandledInterrupt}	; irq18
	dc.l {$82000000+NonHandledInterrupt}	; irq19
	dc.l {$82000000+NonHandledInterrupt}	; irq20
	dc.l {$82000000+NonHandledInterrupt}	; irq21
	dc.l {$82000000+NonHandledInterrupt}	; irq22
	dc.l {$82000000+NonHandledInterrupt}	; irq23
	dc.l {$82000000+NonHandledInterrupt}	; irq24
	dc.l {$82000000+NonHandledInterrupt}	; irq25
	dc.l {$82000000+NonHandledInterrupt}	; irq26
	dc.l {$82000000+NonHandledInterrupt}	; irq27
	dc.l {$82000000+NonHandledInterrupt}	; irq28
	dc.l {$82000000+NonHandledInterrupt}	; irq29

	end				;dahinter eine leere Zeile !