2025-12-04 7:35 PM - last edited on 2025-12-05 5:05 AM by mƎALLEm
New question split from this thread.
Hello,
Thank you for your response. I have double-checked and found that the 6.10 version also cannot be configured in this way. I will adopt the single-line mode on the next hardware version.
However, there is still a question regarding the configuration of can in version 6.16. Why must the sum of the two parameters in the following figure be 32? Otherwise, there will be a warning. In version 6.13, this issue does not exist.
The attachment contains the relevant IOC files.
2025-12-04 11:46 PM - edited 2025-12-05 12:44 AM
Hello @BJX
The CubeMX should allow (TX Buffers Nbr + TX FIFO Queue Elmts Nbr ≤ 32 ) instead of ((TX Buffer Nbr + TX Fifo Queue Elmts Nbr) == 32
A ticket (ID: 222211) has been escalated to the development team to address and correct this behavior.
Regarding this point :"Both TX and RX pins must be assigned simultaneously; otherwise, the UART peripheral cannot be enabled." : MX 6.10.0 and MX 6.16.0 are behaving the same way , in Asynchronous mode both pins are reserved.
THX
Ghofrane
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