2019-08-06 08:43 AM
Hi,
As the title says really. What do the dividers I have highlighted in the screengrab correspond to in the processor? The options in those boxes are "/1" and "/8" and the names "Cortex Div" and "Cortex2 Div" appear when you hover the mouse over them.
The closest I could find was that the Systick divider in the core processor programming manual describes how to calculate the reload value and has either a divide by 1 or 8 depending on whether the source clock is HCLK or external, respectfully. If that is the case then the values I use should always be "/1", correct? Because they are only ever sourced from the same clock as the CPU.
Thanks.
Solved! Go to Solution.
2019-08-06 01:33 PM
Thought the speed selection was in the SYSTICK control registers (internal/external), here presumably for the CPU1(M7) and CPU2(M4)
Poorly documented, but would take a few minutes to test/quantify.
2019-08-06 01:33 PM
Thought the speed selection was in the SYSTICK control registers (internal/external), here presumably for the CPU1(M7) and CPU2(M4)
Poorly documented, but would take a few minutes to test/quantify.
2019-08-07 01:23 AM
Deleted, was meant to be reply.
2019-08-07 01:25 AM
Hi Clive,
You're right. I was looking in the Systick section of the programmering manual for both the CM7 and CM4 and managed to miss it, but I have now found the bit in the Systick control register as you said.
Thank you.