STM32G474RE: Dual-Mode Sampling for ADC pair 3/4 does not function correctly.

[Ethan5]

Hello,

I have an STM32G474RE Nucleo board configured in Dual Regular Simultaneous Mode for ADC 3/4 using CubeMX. I noticed some strange behavior with ADC 4, specifically that its conversions freeze after operating for some length of time. I thought I was experiencing a software problem on my end, but after much testing and ordering another board, I believe the issue is inherent to the STM32G474RE. When I configure a simple test for ADC pair 1/2 with DMA, using Dual Regular Simultaneous Mode and triggered by a timer, and separate the resulting conversions into two 16-bit values in the debugging window, no issues arise. But when I repeat the test and only change the ADC pair to ADC 3 (master) and ADC 4 (slave), the conversions from ADC 4 freeze every time after some length of time. I also noticed that any other code makes the problem worse. For example, if I poll SPI Transmit/Receive in the while loop in main, the readings from ADC 4 freeze almost immediately. I even tested a simple "cnt_var++" in the while loop and observed the same behavior. 

I have since changed the code for my project to only use ADC pair 1/2 but with multiple channels, and it works fine. But, I wanted to see if anyone else has experienced or reported this problem. Thanks!

[Ghofrane GSOURI]

Hello @Ethan5 

Could you please share your .ioc file? This will allow us to review your configuration and help identify any issues in the generated project.

THX

Ghofrane

[mrve]

Hello @Ghofrane GSOURI ,

I see @Ethan5 has not responded yet to your reply. But I actually have encountered the same issue. 

I am experiencing the issue on a STM32G474PEI. I configured two ADC pairs in Dual Regular Simultaneous Mode: ADC1/2 and ADC3/4 using STM32CubeIDE. I configured DMA for both masters (ADC1 and ADC3) so the data of the master and slave will be put interleaved in the provided buffer. All ADCs convert to 12 bit resolution and DMA is configured as WORD size and cyclic. The two ADC pairs will be triggered by the same timer event (TIM3).

I notice that the conversions from ADC 4 'freezes' reproducible after some length of time. The 'freezing' is observed because the sample provided through DMA from that point in time onward does not change.

The moment ADC4 'freezes' seems to occur shortly after HAL_ADC_ConvHalfCpltCallback or HAL_ADC_ConvCpltCallback has been invoked. We perform processing in these ISRs on the captured samples. We initiate transfer of half the data from the buffer to external memory via QPSI using DMA. Maybe this is related.

I have attached the .ioc file.

I hope you can help,
Regards,
Maarten