Trouble setting up the Ethernet MAC on STM32MP255F: failed to reset the dma

[lucasm]

Hi,

We are trying to make use of the ethernet interface in this fashion:

- The board is a custom one with a soldered module from Karo, the qsmp-2550, that includes an stm32mp255fa.

- The eth2 is connected to a PHY (TI DP83869HM) in RGMII.

- The PHY is then configured to output Base100-FX to an SFP cage.

- There is no CLK125, we use ck_ker_eth2 configured at 125Mhz (confirmed in /sys/kernel/debug/clk/stm32_clk_summary), we use the `st,ext-phyclk` DT property.

The PHY is reachable via mdio using the CLI from mdio-tools and seem to be working as intended.

We checked that the PHY sends the correct clock, the RX one, with a scope: it does.

Then when enabling the link using `ip link set up eth0` we are greeted with:

```

root@qsmp-2550:~# ip link set up eth0
[ 16.583371] stm32-dwmac 482d0000.eth2 eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
[ 16.586971] stm32-dwmac 482d0000.eth2 eth0: Register MEM_TYPE_PAGE_POOL RxQ-1
[ 17.123948] stm32-dwmac 482d0000.eth2 eth0: PHY [stmmac-1:00] driver [TI DP83869] (irq=67)
[ 18.135319] stm32-dwmac 482d0000.eth2: Failed to reset the dma
[ 18.135559] stm32-dwmac 482d0000.eth2 eth0: stmmac_hw_setup: DMA engine initialization failed
[ 18.144161] stm32-dwmac 482d0000.eth2 eth0: __stmmac_open: Hw setup failed
RTNETLINK answers: Connection timed out

```

Everywhere we looked points to a clock misconfiguration but for the life of me I can't find which one is missing/wrong.

I attached a full dmesg and device trees for optee (the RCC+RIF part), uboot and the overlay for linux. #include files can be found here if curious: https://github.com/karo-electronics/meta-karo (scarthgap branch).

There are extra lines in the logs due to dyndbg + i added a few printk in the stm32-dwmac driver (at the end of stm32mp2_set_mode) to dump a few variables as well as in the DP83869 driver to see if it is actually configuring the PHY.

[PatrickF]

Hi @lucasm 

I assume you already look carefully to https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration#RGMII_with_Crystal_on_PHY--no_CLK125_from_PHY_-28Reference_clock_-28standard_RGMII_clock_name-29_CLK125_is_provided_by_a_RCC_SoC_internal_clock-29

Dma reset error usually mean missing clock to the GMAC.
Maybe double check the (dump) ETH2_CLK_SEL = 1 and ETH2_REF_CLK_SEL = 0 and ETH2_SEL[2:0] =0b001

double check also pin choices (don't worry yet to GPIO advance configuration)

Regards.

[PatrickF]

Those other posts might help

https://community.st.com/t5/stm32-mpus-embedded-software-and/no-phy-link-with-dp83867-rgmii-on-stm32mp2-missing-125mhz-clock/m-p/822983

https://community.st.com/t5/stm32-mpus-products-and-hardware/dp83867-phy-clock-problem-don-t-bring-up/m-p/208675

Regards.

[lucasm · Accepted solution]

Hi,

It was indeed ETH2_CLK_SEL that was set to 0.

But the reason wasn't the setup, it was the linux fork provided by Karo (the manufacturer of the module we are using) that for some reason patched out those lines:

```
if ((clk_rate == ETH_CK_F_125M) && (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
  dwmac->enable_eth_ck = true;
  val |= SYSCFG_ETHCR_ETH_CLK_SEL;
}
```

into this:

```
if ((clk_rate == ETH_CK_F_125M) && (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
  dwmac->enable_eth_ck = true;
  val |= !dwmac->ext_phyclk * SYSCFG_ETHCR_ETH_CLK_SEL;
}
```

Reverting this change and keeping everything else the same now works.

Sorry for the inconvenience.