STM32MP257 U-Boot bmp display does not work with MIPI-DSI 1-lane panel

[SullyNiu]

Product

STM32MP257DAK3 CPU
Board: Custom board (based on STM32MP257)

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Software Environment

• U-Boot: from stm32mp-openstlinux-6.6-yocto-scarthgap-mpu-v25.08.27

• Boot stage: U-Boot

• Display command: bmp display

• Display interface: MIPI-DSI

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Problem Description

I am using STM32MP257DAK3 with two different MIPI-DSI LCD panels:

1. Panel A: MIPI-DSI 4 lanes
   → Works correctly in U-Boot using bmp display

2. Panel B: MIPI-DSI 1 lane
   → Does NOT work in U-Boot using bmp display

According to the STM32MP25 reference manual, the DSI_PCONFR register supports lane configuration from 1 to 4 lanes.
Therefore, I expect DSI 1-lane mode to be supported by hardware.

However, in U-Boot, the 1-lane panel does not display anything.

Important Clarification

For both panels:

• Device Tree is already adapted separately:

  • Correct dsi,lanes = <4> and dsi,lanes = <1> configuration

  • Separate panel nodes

• Panel drivers are already adapted and validated

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Question / Clarification Requested

I would like to confirm:

1. Does the U-Boot DSI driver (drivers/video/stm32/stm32_dsi.c) officially support MIPI-DSI 1-lane mode?

2. Is there any limitation, missing configuration, or hard-coded lane setting in the current U-Boot implementation that only supports  4-lane panels?

3. Is this a known limitation or known issue in the STM32MP25 U-Boot BSP?

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Additional Notes

• The issue is only observed in U-Boot stage when using bmp display.

• No DSI error is printed in U-Boot console.

• The DSI PHY and clock configuration are shared between both panels.

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Expected Behavior

U-Boot should correctly configure the DSI controller to operate in 1-lane mode.

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Request

Please clarify whether:

• DSI 1-lane mode is supported in U-Boot for STM32MP257

• A patch or workaround is required

• Or if this is a known limitation in the current BSP release

[SullyNiu]

Ticket Update – Additional Debug Information

I have performed additional debugging in U-Boot by directly reading the DSI registers.

• Register DSI_PCONFR at address 0x480000A4

• Value read: 0x00002000

According to the STM32MP25 reference manual, this value corresponds to 1 data lane configuration.

[SullyNiu · Accepted solution]

Answer

Yes, the U-Boot DSI driver (drivers/video/stm32/stm32_dsi.c) officially supports MIPI-DSI 1-lane mode.

I have successfully brought up a MIPI-DSI 1-lane panel in U-Boot on STM32MP25.
After verification:

• The DSI host is correctly configured to 1 data lane

• No hard-coded 4-lane limitation exists in the current U-Boot implementation

• The issue was not a BSP limitation or known issue

The U-Boot DSI driver works as expected for both 1-lane and 4-lane panels, provided that:

• Device tree configuration is correct

• Panel initialization sequence and timing parameters match the panel datasheet