2025-12-24 3:09 AM
Hi,
I am trying to work with the USART6 which is connected to is connected to PF13 (TX) and PF14 (RX) on the extended GPIO.
It looks like the SCRIF does not allow access to this USART, wven though the OPTEE configuration seems to enable it:
from optee/...core/.../stm32mp257f-ev1-ca35tdcid-rif.stdi:
...
IFPROT(STM32MP25_RIFSC_USART6_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS)
...
but when I boot the board I can see this:
cat /sys/kernel/debug/stm32_firewall/rifsc | grep USART
| USART1 || 31 || NSEC || NPRIV || enabled || enabled || 0 || 0x0 |
| USART2 || 32 || NSEC || PRIV || enabled || disabled || 1 || 0x0 |
| USART3 || 33 || NSEC || NPRIV || enabled || enabled || 0 || 0x0 |
| USART6 || 36 || NSEC || NPRIV || enabled || disabled || 2 || 0x0 |
From what I understand it means the CID is 2 which means access to this USART can be done only from the M33 micro.
Is that correct?
How can I solve this? I am struggeling with Yocto for a while with no success.
Thanks.
2025-12-27 10:44 PM
One more log I can see is:
stm32-rifsc 42080000.bus: serial@40220000: Device driver will not be probed
at boot.
Any idea why?
2026-01-29 2:52 PM
Hi @saarpartush
What is the status of USART6?
2026-01-30 12:46 AM
Hello @saarpartush,
Yes, that means that the RIF configuration of the USART you're trying to use does not allow a Cortex A35 access. I guess it's configured with CID2. More information in the Wiki.
I hope it helps,
Gatien