Resolved! On STM32MP1 devices, are 32-bit accesses to SRAM1,2,3,4 atomic?
We would like to share data between the A7-core and the M4-core on an STM32MP1 device. Those cores both have access to the SRAM1,2,3,4 . The M4-core is connected directly via the AHB interconnect, the A7-core is connected via the AXI-based NIC-400 in...