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usart6 serial error setting baudrate
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2025-11-10 8:12 PM - edited 2025-11-10 8:13 PM
hi team,
I'm facing issue in enabling usart6 of the expansion connector of stm32mp257f-ev1,
All i did was to enable the &usart6 via DT overlay, even tried disabling dmas, but no luck.
I have attached the kernel log and also attached the RIFSC debug log FYR
Hoping for a quick reply, thanks in advance.
/dts-v1/;
/plugin/;
/ {
compatible = "st,stm32mp257f-ev1";
fragment@0 {
target = <&usart6>;
__overlay__ {
status = "okay";
};
};
};$ stty -F /dev/ttySTM1 115200
E/TC:0 stm32_serc_handle_ilac:133 SERC exceptions [63:32]: 0x10
E/TC:0 stm32_serc_handle_ilac:139 SERC exception ID: 36
[ 39.106314] SError Interrupt on CPU0, code 0x00000000bf000002 -- SError
[ 39.106336] CPU: 0 PID: 1618 Comm: stty Tainted: G O 6.6.78 #1
[ 39.106344] Hardware name: STMicroelectronics STM32MP257F-EV1 Evaluation Board (DT)
[ 39.106348] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 39.106357] pc : stm32_usart_rx_dma_start_or_resume+0x80/0x234
[ 39.106375] lr : stm32_usart_startup+0x8c/0x130
[ 39.106383] sp : ffff80008352b950
[ 39.106385] x29: ffff80008352b950 x28: ffff000093789080 x27: 0000000000020800
[ 39.106399] x26: ffff800081037828 x25: ffff800081037468 x24: 0000000000000000
[ 39.106409] x23: 0000000000000000 x22: ffff00008c5b5c00 x21: ffff8000819fd088
[ 39.106419] x20: 0000000000000000 x19: ffff800081b19210 x18: 0000000000000001
[ 39.106428] x17: 0000000000000000 x16: 0000000000000000 x15: 0000000000000000
[ 39.106437] x14: 0000000000000000 x13: 006c61697265732e x12: 3030303032323034
[ 39.106447] x11: 0000000000000037 x10: ffff80008112e9b8 x9 : 0000000000000000
[ 39.106457] x8 : ffff00008c52d0c0 x7 : 0000000000000000 x6 : ffff8000819a3ce8
[ 39.106466] x5 : ffff00008246ce08 x4 : ffff00008246cec8 x3 : 0000000000000000
[ 39.106476] x2 : ffff800081e05000 x1 : 0000000000000000 x0 : ffff0000818b2080
[ 39.106488] Kernel panic - not syncing: Asynchronous SError Interrupt
[ 39.106491] CPU: 0 PID: 1618 Comm: stty Tainted: G O 6.6.78 #1
[ 39.106497] Hardware name: STMicroelectronics STM32MP257F-EV1 Evaluation Board (DT)
[ 39.106501] Call trace:
[ 39.106505] dump_backtrace+0x94/0x114
[ 39.106517] show_stack+0x18/0x24
[ 39.106526] dump_stack_lvl+0x48/0x60
[ 39.106535] dump_stack+0x18/0x24
[ 39.106542] panic+0x324/0x380
[ 39.106550] nmi_panic+0x8c/0x90
[ 39.106557] arm64_serror_panic+0x6c/0x78
[ 39.106563] do_serror+0x3c/0x70
[ 39.106569] el1h_64_error_handler+0x30/0x48
[ 39.106578] el1h_64_error+0x64/0x68
[ 39.106584] stm32_usart_rx_dma_start_or_resume+0x80/0x234
[ 39.106592] stm32_usart_startup+0x8c/0x130
[ 39.106600] uart_startup+0x13c/0x2fc
[ 39.106609] uart_port_activate+0x34/0x9c
[ 39.106616] tty_port_open+0x8c/0x13c
[ 39.106625] uart_open+0x1c/0x30
[ 39.106632] tty_open+0x138/0x6dc
[ 39.106639] chrdev_open+0xbc/0x208
[ 39.106649] do_dentry_open+0x1b0/0x524
[ 39.106660] vfs_open+0x2c/0x38
[ 39.106666] path_openat+0xb14/0xdf0
[ 39.106676] do_filp_open+0x9c/0x14c
[ 39.106684] do_sys_openat2+0xc4/0x104
[ 39.106691] __arm64_sys_openat+0x64/0xac
[ 39.106697] invoke_syscall+0x48/0x114
[ 39.106706] el0_svc_common.constprop.0+0x40/0xe0
[ 39.106715] do_el0_svc+0x1c/0x28
[ 39.106723] el0_svc+0x38/0xc8
[ 39.106731] el0t_64_sync_handler+0x120/0x12c
[ 39.106738] el0t_64_sync+0x190/0x194
[ 39.106746] SMP: stopping secondary CPUs
[ 39.106761] Kernel Offset: disabled
[ 39.106763] CPU features: 0x0,00000000,00020000,0000421b
[ 39.106769] Memory Limit: none
[ 39.367284] ---[ end Kernel panic - not syncing: Asynchronous SError Interrupt ]---
CTRL-A Z for help | 115200 8N1 | NOR | Minicom 2.9 | VT102 | Offline | ttyACM0 root@stm32mp25-eval-e3-e4-6a:~# cat /sys/kernel/debug/stm32_firewall/rifsc
=============================================
RIFSC dump
=============================================
=============================================
RISUP dump
=============================================
| Peripheral name || Firewall ID || N/SECURE || N/PRIVILEGED || CID filtering || Semaphore mode || SCID || SEMWL |
| TIM1 || 0 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM2 || 1 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM3 || 2 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM4 || 3 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM5 || 4 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM6 || 5 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM7 || 6 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM8 || 7 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM10 || 8 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM11 || 9 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM12 || 10 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM13 || 11 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM14 || 12 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM15 || 13 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM16 || 14 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM17 || 15 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| TIM20 || 16 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| LPTIM1 || 17 || SEC || PRIV || enabled || disabled || 1 || 0x0 |
| LPTIM2 || 18 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| LPTIM3 || 19 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| LPTIM4 || 20 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| LPTIM5 || 21 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SPI1 || 22 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SPI2 || 23 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SPI3 || 24 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SPI4 || 25 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SPI5 || 26 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SPI6 || 27 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SPI7 || 28 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SPI8 || 29 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SPDIFRX || 30 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| USART1 || 31 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| USART2 || 32 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| USART3 || 33 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| UART4 || 34 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| UART5 || 35 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| USART6 || 36 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| UART7 || 37 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| UART8 || 38 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| UART9 || 39 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| LPUART1 || 40 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| I2C1 || 41 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| I2C2 || 42 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| I2C3 || 43 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| I2C4 || 44 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| I2C5 || 45 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| I2C6 || 46 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| I2C7 || 47 || SEC || PRIV || enabled || disabled || 1 || 0x0 |
| I2C8 || 48 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SAI1 || 49 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SAI2 || 50 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SAI3 || 51 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SAI4 || 52 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| RESERVED || 53 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| MDF1 || 54 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| ADF1 || 55 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| FDCAN || 56 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| HDP || 57 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| ADC12 || 58 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| ADC3 || 59 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| ETH1 || 60 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| ETH2 || 61 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| RESERVED || 62 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| USBH || 63 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| RESERVED || 64 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| RESERVED || 65 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| USB3DR || 66 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| COMBOPHY || 67 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| PCIE || 68 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| UCPD1 || 69 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| ETHSW_DEIP || 70 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| ETHSW_ACM_CF || 71 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| ETHSW_ACM_MSGB || 72 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| STGEN || 73 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| OCTOSPI1 || 74 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| OCTOSPI2 || 75 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SDMMC1 || 76 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SDMMC2 || 77 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SDMMC3 || 78 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| GPU || 79 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| LTDC_CMN || 80 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| DSI_CMN || 81 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| RESERVED || 82 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| RESERVED || 83 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| LVDS || 84 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| RESERVED || 85 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| CSI || 86 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| DCMIPP || 87 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| DCMI_PSSI || 88 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| VDEC || 89 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| VENC || 90 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| RESERVED || 91 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| RNG || 92 || SEC || PRIV || enabled || disabled || 1 || 0x0 |
| PKA || 93 || SEC || PRIV || enabled || disabled || 1 || 0x0 |
| SAES || 94 || SEC || PRIV || enabled || disabled || 1 || 0x0 |
| HASH || 95 || SEC || PRIV || enabled || disabled || 1 || 0x0 |
| CRYP1 || 96 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| CRYP2 || 97 || SEC || PRIV || enabled || disabled || 2 || 0x0 |
| IWDG1 || 98 || SEC || PRIV || enabled || disabled || 1 || 0x0 |
| IWDG2 || 99 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| IWDG3 || 100 || SEC || PRIV || enabled || disabled || 2 || 0x0 |
| IWDG4 || 101 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| IWDG5 || 102 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| WWDG1 || 103 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| WWDG2 || 104 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| RESERVED || 105 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| VREFBUF || 106 || SEC || PRIV || enabled || disabled || 1 || 0x0 |
| DTS || 107 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| RAMCFG || 108 || SEC || PRIV || enabled || disabled || 1 || 0x0 |
| CRC || 109 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| SERC || 110 || SEC || PRIV || enabled || disabled || 1 || 0x0 |
| OCTOSPIM || 111 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| GICV2M || 112 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| RESERVED || 113 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| I3C1 || 114 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| I3C2 || 115 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| I3C3 || 116 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| I3C4 || 117 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| ICACHE_DCACHE || 118 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| LTDC_L1L2 || 119 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| LTDC_L3 || 120 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| LTDC_ROT || 121 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| DSI_TRIG || 122 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| DSI_RDFIFO || 123 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| RESERVED || 124 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| OTFDEC1 || 125 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| OTFDEC2 || 126 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
| IAC || 127 || NSEC || NPRIV || disabled || disabled || 0 || 0x0 |
=============================================
RIMU dump
=============================================
| Initiator name || CIDSEL || MCID || N/SECURE || N/PRIVILEGED |
| ETR || CIDSEL || 1 || NSEC || PRIV |
| SDMMC1 || || 0 || NSEC || PRIV |
| SDMMC2 || || 0 || NSEC || PRIV |
| SDMMC3 || || 0 || NSEC || PRIV |
| USB3DR || || 0 || NSEC || PRIV |
| USBH || || 0 || NSEC || PRIV |
| ETH1 || || 0 || NSEC || PRIV |
| ETH2 || || 0 || NSEC || PRIV |
| PCIE || || 0 || NSEC || PRIV |
| GPU || || 0 || NSEC || PRIV |
| DMCIPP || || 0 || NSEC || PRIV |
| LTDC_L1/L2 || CIDSEL || 0 || NSEC || PRIV |
| LTDC_L3 || CIDSEL || 0 || NSEC || PRIV |
| LTDC_ROT || CIDSEL || 0 || NSEC || PRIV |
| VDEC || || 0 || NSEC || PRIV |
| VENC || || 0 || NSEC || PRIV |
=============================================
RISAL dump
=============================================
| Memory || Subreg. || N/SECURE || N/PRIVILEGED || Subreg. CID || Resource lock || Subreg. enable || Subreg. start || Subreg. end |
| LPSRAM1 || A || NSEC || NPRIV || 0x1 || unlocked (0) || enabled || 0x200c0000 || 0x200c1fff |
| LPSRAM1 || B || NSEC || NPRIV || 0x3 || unlocked (0) || enabled || 0x200c0000 || 0x200c1fff |
| LPSRAM2 || A || NSEC || NPRIV || 0x1 || unlocked (0) || enabled || 0x200c2000 || 0x200c3fff |
| LPSRAM2 || B || NSEC || NPRIV || 0x3 || unlocked (0) || enabled || 0x200c2000 || 0x200c3fff |
| LPSRAM3 || A || NSEC || NPRIV || 0x1 || unlocked (0) || enabled || 0x200c4000 || 0x200c7fff |
| LPSRAM3 || B || NSEC || NPRIV || 0x3 || unlocked (0) || enabled || 0x200c4000 || 0x200c7fff |
root@stm32mp25-eval-e3-e4-6a:~#
Solved! Go to Solution.
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2025-11-16 8:35 PM - edited 2025-11-16 8:39 PM
Thanks for the reply, here is the solution
I realised it was because of the m33 firmware which was accessing the same usart6, based on this thread:
So create a bbappend recipe to disable the service that loads the loading of this firmware
# meta-<your-layer>/recipes-extended/stm32mp2projects/m33projects-stm32mp2.bbappend
SYSTEMD_AUTO_ENABLE:${PN} = "disable"
# the st-m33firmware-load-default.sh script started by
# layers/meta-st/meta-st-stm32mp/recipes-extended/stm32mp2projects/files/st-m33firmware-load.service
# loads the USPPD m33 as defined by the variable DEFAULT_COPRO_FIRMWARE in
# layers/meta-st/meta-st-stm32mp/recipes-extended/stm32mp2projects/m33projects-stm32mp2.bb which uses uart6
# for debug trace of the m33 firmware, which conflits when the A35 core try to access the same uart6
# so to disable the auto start service file defined in
# layers/meta-st/meta-st-stm32mp/recipes-extended/stm32mp2projects/m33projects.inc,
# We are disabling the autostart via bbappend
# To disable in run time you can do
# `systemctl disable st-m33firmware-load.service` and `systemctl disable st-m33firmware-load.service`
# or
# `/sbin/st-m33firmware-load-default.sh stop`
##################################
# Another way to overcome thsi conflict is to completely disable the
# m33copro machine feature
# You must define this below line in layer.conf or else local.conf for priority
# MACHINE_FEATURES:remove = "m33copro"
# If you want to use the above method then add above line as well as
# below mentioned BBMASK in layer.conf/local.conf to apply only one
# method of overcoming the mentioned conflict
# BBMASK += "meta-dt-overlay/recipes-extended/stm32mp2projects/m33projects-stm32mp2.bbappend"
# Below is the more conditional way to do the above line
# BBMASK += "${@' '.join([layer + '/recipes-extended/stm32mp2projects/m33projects-stm32mp2.bbappend' \
# for layer in d.getVar('BBLAYERS').split() \
# if 'meta-dt-overlay' in layer]) \
# if 'meta-dt-overlay' in d.getVar('BBFILE_COLLECTIONS').split() \
# else ''} \
# "
# Alternate method instead of bbmask we can use the m33projects-stm32mp2.bbappend for
# Recipe path: recipes-extended/stm32mp2projects/m33projects-stm32mp2.bbappend
# with SYSTEMD_AUTO_ENABLE:${PN} = "disable"
##################################
---
Any how im facing new issue now, when i enable the usart6, /sbin/stm32_usbotg_eth_config.sh this script which starts the usb ethernet functionality is not working as expected.
2 REPLIES 2
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2025-11-13 2:18 AM
Hi @sanjaysb ,
Enabling an UART might not require an overlay.
If you are on stm32mp257f-ev1 usage and customization of the dedicated project in CubeMX might generate the appropriate DTS
I read
[ 39.106746] SMP: stopping secondary CPUswhich is unexpectable and not related to UART6.
Please check double check your DT
Olivier
Olivier GALLIEN
In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.
In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.
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2025-11-16 8:35 PM - edited 2025-11-16 8:39 PM
Thanks for the reply, here is the solution
I realised it was because of the m33 firmware which was accessing the same usart6, based on this thread:
So create a bbappend recipe to disable the service that loads the loading of this firmware
# meta-<your-layer>/recipes-extended/stm32mp2projects/m33projects-stm32mp2.bbappend
SYSTEMD_AUTO_ENABLE:${PN} = "disable"
# the st-m33firmware-load-default.sh script started by
# layers/meta-st/meta-st-stm32mp/recipes-extended/stm32mp2projects/files/st-m33firmware-load.service
# loads the USPPD m33 as defined by the variable DEFAULT_COPRO_FIRMWARE in
# layers/meta-st/meta-st-stm32mp/recipes-extended/stm32mp2projects/m33projects-stm32mp2.bb which uses uart6
# for debug trace of the m33 firmware, which conflits when the A35 core try to access the same uart6
# so to disable the auto start service file defined in
# layers/meta-st/meta-st-stm32mp/recipes-extended/stm32mp2projects/m33projects.inc,
# We are disabling the autostart via bbappend
# To disable in run time you can do
# `systemctl disable st-m33firmware-load.service` and `systemctl disable st-m33firmware-load.service`
# or
# `/sbin/st-m33firmware-load-default.sh stop`
##################################
# Another way to overcome thsi conflict is to completely disable the
# m33copro machine feature
# You must define this below line in layer.conf or else local.conf for priority
# MACHINE_FEATURES:remove = "m33copro"
# If you want to use the above method then add above line as well as
# below mentioned BBMASK in layer.conf/local.conf to apply only one
# method of overcoming the mentioned conflict
# BBMASK += "meta-dt-overlay/recipes-extended/stm32mp2projects/m33projects-stm32mp2.bbappend"
# Below is the more conditional way to do the above line
# BBMASK += "${@' '.join([layer + '/recipes-extended/stm32mp2projects/m33projects-stm32mp2.bbappend' \
# for layer in d.getVar('BBLAYERS').split() \
# if 'meta-dt-overlay' in layer]) \
# if 'meta-dt-overlay' in d.getVar('BBFILE_COLLECTIONS').split() \
# else ''} \
# "
# Alternate method instead of bbmask we can use the m33projects-stm32mp2.bbappend for
# Recipe path: recipes-extended/stm32mp2projects/m33projects-stm32mp2.bbappend
# with SYSTEMD_AUTO_ENABLE:${PN} = "disable"
##################################
---
Any how im facing new issue now, when i enable the usart6, /sbin/stm32_usbotg_eth_config.sh this script which starts the usb ethernet functionality is not working as expected.
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