Hi ST Team,
I am working on custom MPU board based on STM32MP257F-EV1 reference design.
For our design,reassigned I2C1 from the M33 core to the A35 core using STM32CubeMX.The I2C1 ownership changed from CID2 (M33) to CID1 (A35) in CubeMX.
Corresponding RIF changes are applied in stm32mp257f-ev1-ca35tdcid-ostl-rif.dtsi and enabled I2C1 entry in linux devicetree with clock frequency 400kHz.
During runtime, I2C1 SCL frequency is observed at ~141 kHz, even when:
clock-frequency = 400000
clock-frequency = 100000
On referring clock configuration section in cubeMX, could observe the PLL4 is the parent clock for both I2C1 and I2C2.
I2C2 clock output matches the configured frequency on hardware probing in both frequency (100 and 400kHz).
Whether any additional clock, RIF, or access-controller configuration is required specifically for I2C1 after moving it to the A35 core.Can you please check and help us to resolve the issue.
BSP - openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06 - distribution package
Thanks and Regards,
Kaviya M
