Regarding M33 on stm32mp257

[Aks]

Hello

We are implementing the memory CRC generation sequence as described in the reference manual. According to the documented procedure, the following steps must be executed:

1. Write 0x0 in CRCC[1:0] of RAMCFG_xCCR1 to deactivate the CRC.
2. Write 1 in SRAMHWERDIS of RAMCFG_xCR to disable the hardware erase.
3. Select the buffer size to take into account during the CRC computation by setting
CRCBS[2:0] in RAMCFG_xCCR1.
4. Write 0x1 in CRCC[1:0] of RAMCFG_xCCR1 to activate the CRC.
5. Write 1 in CRCCS of RAMCFG_xCCR2 to start the CRC computation.
The calculated signature is stored in RAMCFG_xCCSR when CRCEOC is set
in RAMCFG_xCSR.

While following this sequence, the CRCEOC flag never becomes set. We have attached the code segment used to trigger the CRC operation and to subsequently start the Cortex-M33 boot process. Could you please review the implementation and confirm whether the initialization flow is correct?

void ConfigRetram(void)
{

/*********************
* 1 Enable ECC
*********************/
RAMCFG_RETRAM->ECCKEY = 0xAE;
RAMCFG_RETRAM->ECCKEY = 0x75;
RAMCFG_RETRAM->CR |= 0x01; // ECC Enable

/*********************
* 2 Hardware Erase
*********************/

// Unlock erase
RAMCFG_RETRAM->ERKEYR = 0xCA;
RAMCFG_RETRAM->ERKEYR = 0x53;

// Start erase
RAMCFG_RETRAM->CR |= RAMCFG_CR_SRAMER;

// Wait until erase is finished
while (RAMCFG_RETRAM->ISR & RAMCFG_ISR_SRAMBUSY)
{
valid_delay_ms(1);
}

FlashToRetram_Copy(0x00020000UL, 9150);

RAMCFG_RETRAM->CCR1 = 0x00; //Deactivate the CRC
RAMCFG_RETRAM->CR = (1<<12); //SRAMHWERDIS is set
//print_reg_info(&RAMCFG_RETRAM->CCR1);
RAMCFG_RETRAM->CCR1 |= 0x070; //128Kbytes
//print_reg_info(&RAMCFG_RETRAM->CCR1);
RAMCFG_RETRAM->CCR1 |= (0x01); //activate CRC
//print_reg_info(&RAMCFG_RETRAM->CCR1);
RAMCFG_RETRAM->CCR2 |= 0x01; //activate CRC
//print_reg_info(&RAMCFG_RETRAM->CCR2);

while ((RAMCFG_RETRAM->CSR & RAMCFG_CSR_CRCEOC) == 1)
{
valid_delay_ms(1);
}

/*********************
* 5 Read and Store CRC Signature
*********************/
crc_signature = RAMCFG_RETRAM->CCSR; // Read computed signature

RAMCFG_RETRAM->CRSR = crc_signature; // Write it to reference signature register

///*********************
// * 6 Finalize CRC Mode
// *********************/
RAMCFG_RETRAM->CCR2 |= RAMCFG_CCR2_CRCFC; // Clear CRCEOC flag

RAMCFG_RETRAM->CCR1 &= ~RAMCFG_CCR1_CRCC; // Clear CRCC bits
RAMCFG_RETRAM->CCR1 |= (0x2U << RAMCFG_CCR1_CRCC_Pos); // CRCC = 0b10 → CRC check mode

}

Additionally, we would like to know if an example project or reference application is available that demonstrates how to properly boot the Cortex-M33. If such material exists, we kindly request access to it.

Thank you for your support.

Best Regards

Akshitha Pattem