2021-12-16 11:16 AM
I tried setting the i2c frequency to less than 20KHz but I got the following error:
[ 1.788573] stm32f7-i2c 40012000.i2c: no solution at all
[ 1.792517] stm32f7-i2c 40012000.i2c: failed to compute I2C timings.
[ 1.798793] stm32f7-i2c 40012000.i2c: Impossible to compute I2C timings.
[ 1.805717] stm32f7-i2c: probe of 40012000.i2c failed with error -1
This is the device tree change:
&i2c1{
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_mx>;
pinctrl-1 = <&i2c1_sleep_pins_mx>;
status = "okay";
/* USER CODE BEGIN i2c1 */
clock-frequency = <10000>;
/* USER CODE END i2c1 */
};
Solved! Go to Solution.
2021-12-16 11:33 PM
Hi @cfilipescu ,
which clock are you using as for I2C ?
This is defined in device tree like:
st,pkcs = <
...
CLK_I2C12_HSI
...
When using pclk (PCLK1 for I2C1/2/3/5), at it's maximum of 104.5MHz, there is a lower i2C frequency limit around 13kHz due to size of prescaler and timing registers in I2C.
Solution should be to use a slower clock for I2C, such a HSI (64MHz, so I2C should go down to around 8kHz) or CSI (4MHz, so, I2C should go down to sub kHz).
I'm interested to know your constrains which need to use such low I2C rate as the standard 100kHz usually fit all cases even when using level translators and weak pull-ups.
Regards.
2021-12-16 11:33 PM
Hi @cfilipescu ,
which clock are you using as for I2C ?
This is defined in device tree like:
st,pkcs = <
...
CLK_I2C12_HSI
...
When using pclk (PCLK1 for I2C1/2/3/5), at it's maximum of 104.5MHz, there is a lower i2C frequency limit around 13kHz due to size of prescaler and timing registers in I2C.
Solution should be to use a slower clock for I2C, such a HSI (64MHz, so I2C should go down to around 8kHz) or CSI (4MHz, so, I2C should go down to sub kHz).
I'm interested to know your constrains which need to use such low I2C rate as the standard 100kHz usually fit all cases even when using level translators and weak pull-ups.
Regards.
2021-12-17 05:56 AM
Hi @PatrickF ,
Thanks for the reply, the I2C clk is at 104MHz, so I will lower it.
The slave device I am trying to use seems to be poorly designed since the original controller is running I2C at 300Hz. Right now it is intermittent at 20kHz.
One other thing I noticed on the scope when probing the original control and device is that the rise time is in the micro seconds 1.5 and even higher. Is that going to be an issue?
Regards.
2021-12-17 06:10 AM
Hi,
thanks for the feedback.
At first look, rise time should not be an issue with your planned reduced frequency (even if out of I2C requirements for 100kHz).
Sound like your bus is heavily loaded/capacitive or have too high pull-up resistor values.
Maybe reduce the pull-up resistor values to 1.5K to get better rise time.
Regards.
2021-12-17 06:29 AM
For sure there are some issues with that device but I don't have control over it so I need to just figure out some settings that work with it somewhat reliably.
2021-12-17 07:03 AM
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