Important update
Following my previous post, we have made some improvements to the issue, but we still need assistance to fully understand and resolve the remaining problems.
We managed to get the SPI2 peripheral communicating through HPDMA to an external DAC.
Compared to the previous setup, the following changes have been applied:
The DMA mode is now Linked List, no longer the standard mode.
The transfer direction is still memory-to-peripheral (TX only).
The DMA request source has been changed to REQUEST_SPI2_TX.
We are now using HPDMA2 (Channel 15) instead of HPDMA1.
TIM3 is no longer used.
TIM15 is used to trigger the DMA–SPI transmission of a single burst (1 word) taken from a 50-word buffer located in memory.
The clock remains at 200 MHz, and TIM15 triggers DMA–SPI transfers at 500 kHz.
An additional timer (TIM4) toggles a GPIO used to latch the DAC output (LDAC) at 500 kHz (update event).
The system initially works, starts the DMA–SPI transfers correctly, and the DAC updates properly. However, after some time (from a few seconds up to a few minutes), the DAC stops updating its output. It freezes on a single value and never recovers unless the system is reset.
Oscilloscope measurements show that the SPI data is still being transmitted correctly and the LDAC signal is still stable and well-timed.
We currently do not understand the following points:
Frequency dependence:
If we reduce the SPI/DMA trigger frequency from 500 kHz to 400 kHz, the system becomes stable and the issue never appears.
The same happens if we trigger the SPI transfer only every two timer update events (effectively ~250 kHz).
Output glitches depending on buffer location:
For testing, we are sending a simple ramp. However, depending on the DMA configuration, the ramp shows glitches or jumps.
We temporarily solved this by moving the buffer from DDR memory to SRAM, which removes the glitches.
Still, we would like to understand why the memory location has such a large effect on the output stability.
The DAC itself is known to work correctly at these speeds (SPI clock = 50 MHz), since it runs reliably on another FPGA-based setup. Therefore, we believe the issue is more likely related to our DMA/SPI configuration rather than the DAC.
We are not using CubeMX for code generation, as it tends to generate unreliable configurations for our setup.
Any hints, examples, or suggestions on properly configuring HPDMA linked-list mode, SPI2, and the timer triggers would be greatly appreciated.
Thanks in advance for your support.
