Hello ST team,
I am studying the flash security mechanisms (RDP, WRP, PCROP) on STM32L476RG and I understand how to configure Option Bytes using STM32CubeProgrammer or firmware.
What I am trying to understand is the hardware-level enforcement flow of Option Bytes:
• During reset / power-up, which hardware blocks read the Option Bytes?
• How are these values propagated to the Flash controller and debug access logic?
• At what point relative to CPU reset release are these protections enforced?
I understand that enforcement happens before user firmware execution, but the reference manual does not describe the internal sequence in detail.
Could you please clarify (at a high level) how Option Bytes are latched and enforced by hardware during the boot/reset sequence on STM32L4 devices?
Thank you.
