Understanding hardware-level enforcement of Option Bytes (RDP) in STM32L476?

[Venkatesh_G]

Hello ST team,

I am studying the flash security mechanisms (RDP, WRP, PCROP) on STM32L476RG and I understand how to configure Option Bytes using STM32CubeProgrammer or firmware.

What I am trying to understand is the hardware-level enforcement flow of Option Bytes:

• During reset / power-up, which hardware blocks read the Option Bytes?
• How are these values propagated to the Flash controller and debug access logic?
• At what point relative to CPU reset release are these protections enforced?

I understand that enforcement happens before user firmware execution, but the reference manual does not describe the internal sequence in detail.

Could you please clarify (at a high level) how Option Bytes are latched and enforced by hardware during the boot/reset sequence on STM32L4 devices?

Thank you.

[Bubbles]

hi @Venkatesh_G,

the OBL as described in the RM is essentially hardwired in the flash interface. It makes sure the OB settings are provided to the respective blocks (PWR, sysconfig, debug) before the CPU reset is released. So when the CPU makes the first move, the OBL is already done.

This is necessary, because the boot address is also determined of the OB.

BR,

J

[Venkatesh-8559]

Hi Bubbles ,

Thank you for the clear explanation. This confirms my understanding that the Option Byte Loader is hardwired in the Flash interface and that all Option Byte settings (including boot selection and security) are latched and enforced before the CPU reset is released.

This answers my question regarding the hardware-level enforcement flow.

Thanks again for the clarification.

Best regards,
Venkatesh