X-Cube STL in STM32H745ZI using IAR CRC area is not flashing while debug

[Lucifer37]

Hi,

I'm working on POST using X-cube STL in stm32h745zit3 using IAR 9.30.1 version, while flashing the code into target STM32 board it showing error in Debug log 

post build command everything is fine, on build it's showing CRC area injected successfully, but while flashing it causing problem.

Debug Log : warnings it showing....

Flash Download warning 4096 out of 4098 bytes from data record CODE : [0x080FF000 - 0x080FFFFFF] will not be flashed.

Basically IAR not injecting CRC in to my target, 

It worked perfectly fine in Nucleo-STM32H745ZI, but when I'm using custom board but code size will be more STM32H745ZIT3

LikerScript : 

/*###ICF### Section handled by ICF editor, don't touch! ****/
/-Editor annotation file-/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/-Specials-/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/-Memory Regions-/
define symbol __ICFEDIT_region_ROM_start__     = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__       = 0x080FFFFF;
define symbol __ICFEDIT_region_DTCMRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_DTCMRAM_end__   = 0x2001FFFF;
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ITCMRAM_end__   = 0x0000FFFF;
define symbol __ICFEDIT_region_AXISRAM_start__ = 0x24000000;
define symbol __ICFEDIT_region_AXISRAM_end__   = 0x2407FFFF;

/-Sizes-/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__   = 0x200;
/**** End of ICF editor section. ###ICF###*/

/* symbols for STL CPU TM12 */
define symbol DCache_line_size = 32; /* fix value for Cortex M7 */
define symbol DCache_set_num = 128; /* fix value for STM32H7 */
define symbol Ram_DCache_set_occurence = (__ICFEDIT_region_AXISRAM_end__ - __ICFEDIT_region_AXISRAM_start__ + 1) / (DCache_set_num * DCache_line_size);
define symbol Ram_DCache_set_displacement = DCache_set_num * DCache_line_size;
define symbol region_RAM_STL_CPU_TM12_start = __ICFEDIT_region_AXISRAM_start__ + DCache_line_size; /* DCache Set n°1 */

define memory mem with size = 4G;
define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
define region DTCMRAM_region      = mem:[from __ICFEDIT_region_DTCMRAM_start__   to __ICFEDIT_region_DTCMRAM_end__];
define region ITCMRAM_region  = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
define region STL_CPU_TM12_region = mem:[from region_RAM_STL_CPU_TM12_start size DCache_line_size repeat Ram_DCache_set_occurence displacement Ram_DCache_set_displacement];

define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };

initialize by copy { readwrite };
do not initialize  { section .noinit };

place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region   { readonly };
place at address mem:__ICFEDIT_region_DTCMRAM_start__ { section backup_buffer_section };
place in DTCMRAM_region   { readwrite, block CSTACK, block HEAP };
place in STL_CPU_TM12_region { section stl_cpu_tm12_section };