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Why PSRAM is slower than SRAM and how can one increase the speed of PSRAM in STM32L4R8I.

Associate II


I am capturing an image on OV5640 Camera module. My camera is connected with STM32L4R9I over DCMI protocol. I am further using DMA1 to take image data and store it in PSRAM (with the help of FMC). From PSRAM, image data is being written on SD card. 

Main Problem:

OV5640 datasheet says, "OV5640_JPEG_CTRL07" can have values between 0x02 till 0x37. Here smaller value means higher quality image. However, when I try to store 0x02 value in the register, the captured image when opened in windows using sd card reader says "Unsupported image format". The minimum value i can store in the register is 0x0C (At this value, image is can be opened and seen in the pc). Also note that, this value (0X0C) works fine for 1080p resolution. As soon as i chnaged the camera resolution to 5MP then the same value (0X0C) gives me corrupt image and same issue of "Unsupported image format". 

Solutions, I tried:
I have used different image viewer software to open the image and also used image recovery software but none of them worked out.

Catching Point:

While exploring datasheet of STM32L4R9I, I got to know that AHB2 bus runs on 120MHz and it might be possible my PSRAM is not meeting this 120MHz threshold specifically at higher image size (i.e. at 5MP and good quality factor (using 0x02) value in OV5640_JPEG_CTRL07 register).


I am confused and as i am beginner so i dont know really about this, if someone can help me out to debug the main problem so that i can get high resolution of image at 5MP and using 0x02 value in the OV5640_JPEG_CTRL07 register. And also correct me if my observation is correct or not regarding PSRAM's slower than AHB2 clock speed of 120MHz. 

ST Employee

Hello @Majeed and welcome to the Community 🙂,

Are you using other peripherals with same DCMI bus "AHB2"?

According to the datasheet the maximum AHB clock frequency is 120 MHz. However the FMC_CLK is depend on VDD and CL.

For example, for 2.7 V ≤ VDD ≤ 3.6 V, maximum FMC_CLK = 60 MHz for CLKDIV = 0x1 and 54 MHz
for CLKDIV = 0x0 at CL = 30 pF.

Also, I advise you to refer to the AN5020 table 2 to check the maximum frequency of AHB2 and FMC SRAM .


Thank you.



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