What is the best PLL configuration for H533 ?

[Kraal]

Hi there,

I'm starting to use the NUCLEO-H533RE board to evaluate the H5 device family.

RM0481 has some errors on the PLL configuration:
Fig.55 on page 461 shows a VCO range 0 between 128 and 560 MHz, but the description of bit 5 of register PLL1CFGR (page 492) says 192 to 836 MHz, which is quite different. Which one is the correct one, please ?
Section 11.8.12 name is incorrect page 497 (PLL1 written instead of PLL2).

Regarding the best PLL setup:
For the PLL1RGE possibilities, it select the input frequency range: between 1 and 2, between 2 and 4, between 4 and 8 and between 8 and 16 MHz. What would be the best choice for a input frequency of 8 MHz: between 4 and 8 or between 8 and 16 ? And if possible, explain why that is.

Thank you,
Kraal

[mbarg.1]

If you are new to H5, let STM32Cubeide do it for you - use fix clock problem button.

PLL are something not trivial, you need optimum values to achieve good tradeoff between phase noise and power consumption.