What is the best PLL configuration for H533 ?

[Kraal]

Hi there,

I'm starting to use the NUCLEO-H533RE board to evaluate the H5 device family.

RM0481 has some errors on the PLL configuration:
Fig.55 on page 461 shows a VCO range 0 between 128 and 560 MHz, but the description of bit 5 of register PLL1CFGR (page 492) says 192 to 836 MHz, which is quite different. Which one is the correct one, please ?
Section 11.8.12 name is incorrect page 497 (PLL1 written instead of PLL2).

Regarding the best PLL setup:
For the PLL1RGE possibilities, it select the input frequency range: between 1 and 2, between 2 and 4, between 4 and 8 and between 8 and 16 MHz. What would be the best choice for a input frequency of 8 MHz: between 4 and 8 or between 8 and 16 ? And if possible, explain why that is.

Thank you,
Kraal

[mbarg.1]

If you are new to H5, let STM32Cubeide do it for you - use fix clock problem button.

PLL are something not trivial, you need optimum values to achieve good tradeoff between phase noise and power consumption.

[STOne-32]

Dear @Kraal ,

Thank you for reporting these two typo issues:

1) The correct one is:   VCO range 0 between 128 and 560 MHz

2)  Section 11.8.12 name is incorrect page 497 (PLL1 written instead of PLL2).

These two typos are logged in our internal defect system with reference #222822

Now, regarding the question

" For the PLL1RGE possibilities, it selects the input frequency range: between 1 and 2, between 2 and 4, between 4 and 8 and between 8 and 16 MHz. What would be the best choice for an input frequency of 8 MHz: between 4 and 8 or between 8 and 16? And if possible, explain why that is."

The information can be deduced from the Datasheet : Datasheet - STM32H523xx - Arm<Sup>®</Sup> Cortex<Sup>®</Sup>-M33 32-bit MCU + TrustZone<Sup>®</Sup> + FPU, 375 DMIPS, 250 MHz, 512-Kbyte flash, 272-Kbyte RAM

Go to Table 46. PLL characteristics (wide VCO frequency range) and Table 47. PLL characteristics (medium VCO frequency range) 

Example to reach 250MHz , VOS0 should be used and so "medium VCO frequency range"  in Normal Mode in your case with 8MHz or less using the prescaler before that block to have 8MHz or 4MHz or even 2MHz.  and so lock time is optimized.  Jitter (cycle to cycle and long term also ) is to be considered if Audio or ethernet are used at your final application.

Hope it helps you.

STOne-32.

[Kraal]

@mbarg.1 Thank you for taking the time to answer. However, letting Cube do the work will not help me to understand why it configured the PLL that way. Your second sentence is more interesting expect it does not give enough details for me. If you have pointers to some documentation that I can read (other than the RM and the datasheet), that would be great.

@STOne-32 Thank you for the explanation, especially for the jitter aspect of things (audio is mentionned in the RM, but not ethernet, and I would not have thought of it). My question is still not answered though: if the clock input of the VCO is 8MHz, which PLLxRGE setting shall I use ? 4 to 8, or 8 to 16 ?

Best regards.

[STOne-32 · Accepted solution]

Dear @Kraal ,

Recommendation to use in your case with 8MHz:

10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz.

Another Alternative also is to use the /M pre-scaler and set it to 4 or 2 to have PLL input 2MHz or 4MHz.

My recommendation to have /M = 4 and have PLL input at 2MHz.  This is the Optimum Configuration to reach highest frequency and best Jitter.

Hope it helps you

STOne-32.

[Kraal]

Thank you @STOne-32 . It helps.

Best regards,

Kraal