In RM0456 section 73.4.3 OTG_HS core (p.3279) I found the following statement:
"The OTG_HS receives the 60 MHz clock from the reset and clock controller (RCC). This is typically generated in the PLL associated with the HS PHY and enabled in the RCC. This clock is used for driving the 60 MHz domain at high-speed (480 Mbit/s) and must be enabled prior to configuring the OTG core."
I try to configure STM32U5A9 MCU with CubeMX, but I find no option to configure USB 60MHz clock.
The only available clock setting called "OTG HS Clock" cannot be set to a value larger 32HMz and probably needs to match setting under "Pinout & Configuration" where this time it is called "Ref Clock selection" - see screenshots below.
Please advise. I am a bit confused.
Solved! Go to Solution.
@waclawek.jan An update. I realized that:
1. Probably missing config can be accomplished with the below HAL LL function not used in CubeMX generated code.
2. Probably no additional 60MHz clock config is required. The only required clock config is done in __HAL_RCC_USBPHY_CONFIG macro or directly using RCC_CCIPR2.OTGHSSEL register field (RM0456, section 11.8.47). In HAL RCC_CCIPR2_USBPHYCSEL named is used, probably so nobody can quickly figure out this is the same register and field. RM0456 section 73.4.3 is quite misleading with that respect.
Just a side note for anyone who might come across this topic. OTG_HS host may not be currently fully implemented in HAL. See stm32u5a9xx.h USB_OTG mess · Issue #31 · STMicroelectronics/STM32CubeU5 (github.com)