The USB buffer size of an endpoint does not necessarily need to be equal to the max packet size, However, it is recommended to allocate at least two (largest packet size / 4) + 1 spaces to receive back-to-back packets as mentioned in RM0433, This allows the USB to receive the subsequent packet while the previous packet is being transferred to the CPU.
Hope that helps!
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(first maybe I should say I am working on a USB device implementation, not host, and not using double buffering at the moment)
I am looking at RM0481 (working with STM32H563 at the moment). I saw I think the section in RM0433 you mentioned but I am not familiar with H7 and this manual. I am still a bit confused. So the packet buffer only holds the host-to-device data of SETUP/OUT transactions (the payloads of DATA packets in these transactions) and the device-to-host data for IN transactions (again the payloads of DATA packets), correct ?
When you say two spaces, I guess it means two (DATA) packets, so 2*largest packet size, is the formula (largest packet size/4) + 1 due to H7's architecture (I saw there is a FIFO etc., I am not familiar with H7) ?
My understanding is that the packet buffer is read/written after a SETUP/OUT/IN transaction is finished, and only one DATA packet is either sent or received when a transaction is finished. I understand another transaction can happen meanwhile so it makes sense to have a space for second, but in order to receive a second transaction first the endpoint should be enabled again because it automatically moves to NAK state. So my understanding is when a transaction is finished, the data is transferred in/out from/to packet buffer first, then the endpoint status is updated. In this case, I dont see the benefit of having a larger packet buffer (than the maximum packet size) because it is not possible for hardware to use it due to endpoint state, and again my understanding is that the hardware always start from ADDR_RX and ADDR_TX locations when a matching SETUP/OUT/IN PID is received (so not possible to use it for a second transaction without overwriting for RX or sending the same data for TX).
Maybe I should revise my question, the packet buffer can naturally be more than the max packet size for some reason maybe because the software is designed to work like this (modifying the ADDR_TX,ADDR_RX for subsequent transactions etc. similar to double buffering), but my question is: can the hardware use (or require) a packet buffer more than the max packet size (max payload size in a DATA packet) in one transaction ? and also I guess making it smaller than the max packet size is definitely not recommended ?