2024-01-23 09:56 AM
Hopefully this is more of a sensible non-noob question, it relates to interrupt handling, in my case a simple USART receive interrupt.
I can see how the CubeMX tool is managing the .c file, its created an interrupt handler, for me to insert my code, thats easy. I can detect the interrupt and spit out a short string in response, so its working - all good.
The question I have is, what can I do inside that ISR safely. Do I need to preserve any registers. My aim is to throw anything I receive into a ring buffer of some form, with a view to building a received packet of data. At some point I will need to pick up each completed packet from a list. In order to do that I will possibly need to allocate some memory, and it would be useful if I do not have to put the whole implementation of that ISR in the file that is being auto-generated, so would be handy to also be able to call a function where I can contain the implementation of the ISR in its own compilation unit.
One other question is that of controlling interrupts. At some point, I would have a packet of data in a buffer somewhere that I would access from the main loop of the code. In order for me to safely access that packet from the receive buffer, I would need to first, stop/pause/prevent the next interrupt from interrupting me. On x86 architecture this is quite tricky as you have to rely on the atomic behaviour of specific instructions, and prevent the interrupt in a way that, should an interrupt occur while getting the data safely from the buffer, the interrupt controller will hold/queue that interrupt until the interrupts are re-enabled.
What is the right semantics for doing this on the STM32 platform?
As ever, any help at all much appreciated.
Gerry
2024-01-31 06:49 AM
First hit on google for "does cortex m4 save registers on isr entry" explains that yes, it does in fact save registers on isr entry. The second and third hits also state the same thing.
https://www.embedded.com/programming-embedded-systems-how-interrupts-work-in-arm-cortex-m/
2024-01-31 07:27 AM
As every, very helpful. That is actually a great tutorial series... bookmarked for consumption, thank you for the link.
A couple of videos on is this one covering the read-modify-write race condition I was referring to, and provides the answer in the form of using a processor intrinsic to disable interrupts around the critical sections of code, that is exactly what I was looking for - brilliant!
https://www.youtube.com/watch?v=3ha72Y8pyD4