Unexpected Comparator Output During LoRaWAN and ADC Activity

[Mounika_Navtech]

Hello ,

I am working with comparators on the STM32L496VGT6 microcontroller.
In my setup:

• COMP1 is configured for rising-edge detection.

• COMP2 is configured for falling-edge detection, forming a window comparator arrangement.

• One input of COMP1 is connected to an ADC voltage (through a 2:1 voltage divider).

• The other input is from the DAC internal connection, operating in sample-and-hold mode with the output buffer disabled.

• The outputs of COMP1 and COMP2 are routed to external GPIO interrupts.

• Hysteresis is set to medium.

Voltage levels:

• VH = 0.55 V (corresponding to Vin = 1.1 V after 2:1 divider)

• VL = 0.275 V (corresponding to Vin = 0.55 V after 2:1 divider)

Issue description:
When the input voltage is close to the threshold (around 1.05–1.07 V and 0.51–0.54 V), I observe continuous false comparator interrupts instead of a single expected trigger.

To mitigate this, I increased hysteresis from medium to high and reduced the number of hold cycles from 64 to 32. This helped reduce the issue, but during LoRaWAN transmission, I still observe false comparator triggers.

I have also implemented blanking before each LoRaWAN transmission by calling:

HAL_TIM_OC_Start();

and stopping it after transmission using:

HAL_TIM_OC_Stop();

Despite this, at least one false trigger still occurs during each LoRaWAN transmission, and I also observe similar false glitches during ADC readings. I have attached the schematic files for your reference; kindly review them and suggest possible causes.

I would like clarification on the output compare timer configuration for comparator blanking, and any additional suggestions to eliminate these false triggers during LoRaWAN activity.

Any guidance or recommendations  would be greatly appreciated.

Thank you,
Mounika Ambati