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The PWM signal that has passed through the level shifter(level converter) is not clear.

interactics_ST
Associate III

I'm using PWM with level shifter(BSS138, 74HCT14D, TXB0104) for developing IC embedded LED (such as WS2812)

 

However, when I captured this siganl using scope, I found that the signal was not clear.

Below are the pictures that I captured.

 

1. Before addition of level shifter

 

 

 

interactics_ST_1-1716276134256.png

 

 

2.  After additon FET level Shifter 

 

interactics_ST_7-1716276626683.png

interactics_ST_2-1716276248378.png

 

 

3. 74HCT14 Level shifter

interactics_ST_4-1716276325647.png

4. IC Level shifter (TXB0104)

interactics_ST_5-1716276361854.png

 

Q1

One thing I curious about is that why IDEL signal is in High instead of LOW when using FET level Shifter?

When I tested FET level shifter using non-STM32(ESP32), the Idle signal was LOW, not Hi.  It is a very weired situtation!

 

Q2

And also, according to BSS138 datasheet, T_rising is 18ns. However, in my case, It was longer than specification.

interactics_ST_8-1716277117321.png

 

 

 

PS. I'm using PA0 Pin for PWM control with DMA

1 ACCEPTED SOLUTION

Accepted Solutions
Muhammed Güler
Senior III

I would like to welcome you to the world of high frequency electronics. Even though you don't work with that high of frequencies.

Oscillations caused by impedance mismatch can be seen during polarity transitions.
To reach the values ​​in the datasheet, you need to make the connection via impedance-controlled paths.

https://www.youtube.com/@RobertFeranec/videos
A lot of things are explained on this channel, I recommend you to check it out.

View solution in original post

3 REPLIES 3
Muhammed Güler
Senior III

I would like to welcome you to the world of high frequency electronics. Even though you don't work with that high of frequencies.

Oscillations caused by impedance mismatch can be seen during polarity transitions.
To reach the values ​​in the datasheet, you need to make the connection via impedance-controlled paths.

https://www.youtube.com/@RobertFeranec/videos
A lot of things are explained on this channel, I recommend you to check it out.

AScha.3
Chief

>One thing I curious about is that why IDEL signal is in High instead of LOW when using FET level Shifter?

Maybe G-S puzzeled . 🙂 (or just wrong connected.)

AScha3_0-1716294476642.png

>And also, according to BSS138 datasheet, T_rising is 18ns.

see ds ... at 290mA + 6 ohm drive ! 

But you drive (3V /10k -> ) 0.3 mA , so mosfet + stray  capacities dominate at so low current.

+

Why not using HCT gate as level shifter ? I use e.g.  74AHCT1G86 for such , ( xor, so 2. in on gnd, -> non inverting).

If you feel a post has answered your question, please click "Accept as Solution".

Thank you so much.

 

As you told me, It was a kind of impedance mating problem

So, My colleague and I changed the register's value and added some L and C. After that, It worked and published clean PWM signals which have definitely 5V in level after passing the shifer module.

 

From now, I'm trying to find out the reasons why STM32 MCU has different characteristic on I/O compared to other MCU such as ESP32 and Atmel.