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Strange delay on loading USART TX shift register

risingedge1
Associate II

Hi. I am developing a device for working with real-time industrial interfaces based on RS485. I expect to get a delay of no more than 11 tbits (standart UART frame) + parsing execution time (few microseconds). I am using UART with IDLE IT and master DMA controller (DMA as flow controller). Device based on STM32F411CEU6. I have the following config:

  • DMA1_Stream6 as DMA TX connected to USART2
  • DMA word size 8 bit
  • DMA as flow control
  • USART config: 9(include parity)E1 (8E1), baud rate 9600..12M
  • MCU CPU CLK 100Mhz, APB1 CLK (USART2 source) 50Mhz

start transmit function: 

void pb_tx_config(uint8_t * pbuf, uint8_t size) {

	// dis
	DMA1_Stream6->CR &= 0xFFFFFFFE;

	// config
	DMA1_Stream6->PAR = (uint32_t)&USART2->DR;
	DMA1_Stream6->M0AR = (uint32_t)pbuf;
	DMA1_Stream6->NDTR = size;

	// clear iflags
	DMA1->HIFCR |= 0xFFFFFFFF;
	DMA1->LIFCR |= 0xFFFFFFFF;

	// en
	DMA1_Stream6->CR |= 0x00000001;

}

 Final setup USART & DMA before start transmitting (USART baud rate 9600 with OVER8 = 0):
DMA_USART.jpg

When i starting transmit, i have delay between call pb_tx_config and real start UART TX shifting. This delay ~ 1 UART frame (11 tbit):

UBR.jpg

This delay huge problem for me, because response time increase by another 11 tbit. Please help me to sort out the reason for the appearance of this delay. Thanks...

1 ACCEPTED SOLUTION

Accepted Solutions

Okay, after set TE bit UART (UART complete configured and enabled before) generate IDLE frame + 1 tbit delay. This things described in reference manual, i'am missed this moment... 

View solution in original post

7 REPLIES 7
TDK
Guru

Is this immediately after initializing UART? An idle character is sent when TE is set.

Typically, the UART would be initialized once, and then stay initialized when powered up. You don't need to re-initialize on every transmission.

If you feel a post has answered your question, please click "Accept as Solution".

UART was configured at once, at power up. I just configure DMA Stream at each tx request and this is happening (delay). I am tried clear TE and TXE bits in UART SR reg, but no effect... I still have suspicions about TC & TXE bits, may be i use invalid sequence for clearing... TXE event generate DMA request, this bit must be zero before start and TC bit must be zero, but... while I was writing the answer I noticed that my SR = 0xC0 -> TC &TXE = 1... Okay, my clearing not work. may be this solve. I try again. Of course if that's the problem... Thank you)

risingedge1_0-1700677272639.png

 

TDK
Guru

This edge shows the UART wasn't idle just prior to entering the routine, which is why I thought maybe it was just configured. Perhaps it's still busy shifting out the last character. You could show more of the plot before entry to pb_tx_config to confirm it's done sending the last character.

TDK_0-1700679668402.png

> I am tried clear TE and TXE bits in UART SR reg, but no effect

How? TXE should not be cleared. Guessing you meant TC and not TE. Don't think clearing TC is necessary, although it shouldn't affect things.

If you feel a post has answered your question, please click "Accept as Solution".

It first transaction, i configured UART and immediately call tx function. And yes, i mean TC bit, not TE, sorry. I cant show you all debug things at now. Okay, UART was just configured and I'm calling DMA transfer function. But UART is busy, why? Apparently it's about the TC & TXE bits?

> Okay, UART was just configured and I'm calling DMA transfer function. But UART is busy, why?

As stated above, if you just configured UART, an idle character is sent. It's not about TC or TXE.

If you feel a post has answered your question, please click "Accept as Solution".

Okay, after set TE bit UART (UART complete configured and enabled before) generate IDLE frame + 1 tbit delay. This things described in reference manual, i'am missed this moment... 

I said that twice...

If you feel a post has answered your question, please click "Accept as Solution".