STM32U031 freezing IWDG counter in STOP 0 mode.

[suresh kumar1]

Hello Everyone,

I am facing an issue with my MCU entering low-power mode.

My idea is to freeze the Independent Watchdog (IWDG) counter in STOP mode so that the MCU will not reset due to the IWDG counter elapsing.
From my understanding, this can be achieved by clearing bit 17 (IWDG_STOP) of the FLASH_OPTR register, if I am right.

As per the reference manual, in STOP mode, the IWDG can be automatically frozen depending on the configuration of the IWDG_STOP bit in the FLASH_OPTR register.
So, the IWDG should not reset the MCU during STOP (sleep) mode, correct?

If both assumptions are correct, could you please share the steps or example code to:

1. Configure the IWDG to operate (or be frozen) in STOP mode, and

2. Set up the FLASH_OPTR register appropriately for this behaviour?

[TDK]

Setting IWDG_STOP = 0 will make IWDG counter frozen in stop mode, yes.

You can set option bytes using STM32CubeProgrammer, in the OB tab.