Hello,
I am reading 6.3.30 LCD-TFT controller (LTDC) section to interface with DS90C385A (LCD) or ADV7125 (VGA)
Assume that LCD Clock (pixel clock) polarity is set to high. Ideally, we can expect rising edge of clock aligned to the middle of the data. But I can see there is a more time for setup and less time for hold. Refer the figure 46 of datasheet.
Note: I am going configure pixel clock low for DS90C385A (LCD) and high for ADV7125 (VGA). Also, I need to ensure HW work till 150MHz clock.
