STM32H753xI - LCD-TFT controller (LTDC) timing diagram

[vinoth_ta]

Hello,

I am reading 6.3.30 LCD-TFT controller (LTDC) section to interface with DS90C385A (LCD) or ADV7125 (VGA)

Assume that LCD Clock (pixel clock) polarity is set to high. Ideally, we can expect rising edge of clock aligned to the middle of the data.  But I can see there is a more time for setup and less time for hold. Refer the figure 46 of datasheet. 

Note: I am going configure pixel clock low for DS90C385A (LCD) and high for ADV7125 (VGA).  Also, I need to ensure HW work till 150MHz clock. 

[KDJEM.1]

Hello @vinoth_ta and welcome to the community;

According RM0433 Rev 8 Programmable polarity section "The horizontal and vertical synchronization, data enable and pixel clock output signals polarity can be programmed to active high or active low through the LTDC_GCR register"
 In the datasheet section 6.3.30 LCD-TFT controller (LTDC) characteristics, can find measurements of the LTDC characteristics with a specific configuration.

To use the LTDC, I recommend you to start by looking at Introduction to LCD-TFT display controller (LTDC) on STM32 MCUs - Application note may help you.

Thank you.

Kaouthar

[vinoth_ta]

Thanks for your response. I will rewrite my question other way. 

 I am interface STM32 with DS90C385A (LCD). The MCU can have data output hold time th(DATA) of 0 ns. But the chip DS90C385A needs hold time of min 0.5ns. Assume that clock and RGB data length matched to 0 ps delay. 

I am hoping for high chance of timing violation if we do the 0ps length matching. Is it make a sense?

[KDJEM.1]

Hello @vinoth_ta ;

According to the datasheet, the minimum data output hold time is 0ps but the maximum data output hold time is not limited.

Thanks to its timings and hardware interface flexibility, the LCD-TFT controller is able to drive several monitors
with different resolutions and signal polarities. There is no risk if you make the correct length matching.  

Thank you.

Kaouthar