STM32H743 ADC values fluctuating after voltage divider

[Jonah9Veh]

I have a +30V -30V input to be fed to STM32H7 ADC 16-bit

I tried using a 2 resistor potential divider using 33K 3.3K ; 1K 100E, 1M 100K, resistor combinations but the output is not correctly read by the ADC. (For 3V input, ADC reads from 2.2V to 3.2V randomly fluctuating) Not constant

But if I bypass the divider circuit and feed an input less than 3.3V to the ADC pin directly, it reads perfectly (For 3V input, it reads 2.9999).

Should sampling time affect the resistor values? 

[TDK]

The ADC must be calibrated using HAL_ADCEx_Calibration_Start prior to using it.

ADC example project:

https://github.com/STMicroelectronics/STM32CubeH7/blob/fa7b5c9279009b6876fb186892a45c4256dd239b/Projects/NUCLEO-H743ZI/Examples/ADC/ADC_OverSampler/Src/main.c#L128

[Jonah9Veh]

@unsigned_char_array 

VSSA is to the same GND_D as VSS. Refer SCH below. 

@TDK 

Yes, we have calibrated it using HAL_ADCEx_Calibration_Start 

@MasterT 

Buffer output from the opamp is connected to ADC_INP_1 using a wire. Any reasons for series resistance to be 10-50 Ohm from OPA output.

[MasterT]

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@MasterT 

Buffer output from the opamp is connected to ADC_INP_1 using a wire. Any reasons for series resistance to be 10-50 Ohm from OPA output.

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Resistor is to isolate capacitive load 0.1-1 uF. 

From the start:

1. SAR ADC Dictates of capacitor across it's input. The value of cap determined by highest freq. of input signal, so for pure DC input - 1uF is optimal, but can be up to 10.

2. Because of this cap, OPA buffer needs  resistor in series for stability. The min value R is from OPA datasheet..

Max limited to : sampling rate and linearity requirements

[unsigned_char_array]

So GND_D is not digital ground, but also analog ground? I recommend filtering the analog power supply, filtering VREF+ and connecting the analog ground to digital ground on 1 spot. Right now both VDDA/VREF+ w.r.t. VSSA and VDD w.r.t VSS have the same ripple as they are in parallel.
I recommend not connecting the VREF+ to VDD.

[TDK]

You said you see 1 V of noise, but the data you present shows around 0.01 V of noise.

[Jonah9Veh]

@TDK 1V is considering those intermittent spikes with some earlier tests I did. At times the values shoot up or down. Below image shows that it is nearly of 0.1. And it is erratic. Need to get rid of that. What could be the possible reason?

[unsigned_char_array]

I think we already concluded it's not the signal source. So it must be in the circuit and in the wiring.
Any noise or ripple on the VREF+ will effect the measurement. You use an unfiltered power supply for VDDA and VREF+ and use long wires. I recommend filtering the analog power supply with a ferrite bead and a capacitor.

[TDK]

These are likely due to volatility in the VREF+ rail.