2024-07-18 03:54 AM
Hallo,
we are using STM32H735G-DK boards and wondering whether unaligned access of memory mapped HyperRAM should be generally possible or not.
In the errate sheet for the STM32H735
there are two issues which may indicate that unaligned access of HyperRAM is not possible:
A) OCTOSPI: 2.8.4 Odd address alignment and odd byte number not supported at specific conditions
In the table it says, that memory-mapped read and memory-mapped write should be possible when the HyperRAM is connected via HyperBus. So this errata should not apply as STM32H735G-DK examples are using HyperRAM in HyperBus mode, or does it?
B) FMC: 2.7.3 Unsupported read access with unaligned address
Read access with unaligned address, such as a half-word read access starting at odd address, is not supported.
Workaround: Compile the software that accesses the fmc region with a compiler option that ensures data alignment, such as –no_unaligned_access
This should only apply when connecting memory via FMC, so should not be an issue, should it?
Are there any other known issues, why unaligned access to HyperRAM on the STM32H735G-DK should not be possible?
We are currently facing read errors when doing unaligned memory access in HyperRAM on the STM32H735G-DK, so we would be glad to know, if unaligned access should be generally possible or not.
We also tried various MPU settings of the HyperRAM region but could not find a setting which allowed unaligned memory access. Either we get a HardFault (which is ok, for some MPU settings) or we are reading wrong values from unaligned locations.
Thanks in advance!
2024-07-29 01:20 AM
Hello @rk_iot ,
Please make sure that the DQS is enabled. And also, at least six cycles memory latency must be set when DQS is used for HyperBus™ memories as mentioned in the errata sheet.
Thank you.
Kaouthar
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