Experimenting with STM32F427 and STM32F446 I found out, that the RCC_CR.HSEBYP bit is *not* reset by Software reset. It is reset only by NRST and Power-On reset.
While applications where this could lead to problems (i.e. where HSE clock source is changed on-the-fly and software after performing Software reset relies on reset state of this bit) are probably very rare, it may result in an "interesting" surprise if one stumbles upon it, and deserves to be documented.
Can ST please confirm/explain and document?
Thanks,
JW
