QUAD-SPI too busy!

[Albi G.]

Hi guys,

i am using the QuadSPI periphery to interface with a FPGA. I am in need of raw throughput with alternating write and read cycles of some number of bytes. I am just concept-prooving right now.

Since QUADSPI->CCR is not allowed to be modified when BUSY==1 the busy flag effectively limits the command rate - which is useful since i obviously need to wait to finish a a command before sending the next one.

My configuration is:

• 4 bit wide Instruction
• Skip directly to 4bit wide Data-transfer
• Min CS-High time = 0 (1 cycle)
• IndirectRead / IndirectWrite mode, no DMA for now.

Now, unfortunately the BUSY flag is rather lame and it takes exactly 6-7 clocks after CS rises that the BUSY flag clears. That is really **** ** the achievable command rate!

With 6-7 clocks, i mean periphery-clocks after the prescaler. (@1MHz SPI clock, the BUSY-signal is 1 for 6µs after CS rises. If 10MHz is used, then its 0.6us)

What i dont understand is, that this behavior makes the minimum CS-high setting kind of useless. (i never achieve a scenario where CS is less than 6 cycles high in-between commands)

This holds true for consecutive reads, consecutive writes, and alternating read-write.

What could go wrong ??

This is my example code. Not using the library, but my code hopefully reads kind of intuitively...

Measured though my Debug-GPIO: 16.7µs from Command start to BUSY=0

Chip select Low for 11µs

Give me a faster BUSY, please

BTW: i also get the same behavior if i configure the QSPI differently:

• skip Instruction
• Send one byte address
• skip directly to Data

== Same timing(-problems)

thanks

[S.Ma]

if miso and mosi swap controo bit is available, it might not do what you expect.

[Tesla DeLorean]

One of the other potential pitfalls of using the QSPI/FMC external interfaces for things like FIFO's or state-machines is that the core/peripheral can do funny things with unaligned access, bursts access, speculative reads, and reads which are abandoned and retried.

[Arnon]

Those "funny things" is what made go and look at the CS and clock.

I would never imagine that clock could start before CS goes down....

[Singh.Harjit]

Please stop; this is not cool. I'm sure they are decent, hard working people doing their best.

[berendi]

I am sure they are decent people who work to the best of their abilities. That they lack some education, practice, and can not understand the task assigned to them is not their fault.

By the time they get more practice, knowledge and language skills on the job, they will be able to move on to properly paid jobs, and ST (or maybe its shady contractor) can hire the next batch of inexperienced fresh graduates on the cheap.