Hello ST Experts,
I am using an STM32H755ZIT6 with W25Q256JV flash in Quad-SPI mode at 100 MHz.
On our latest hardware revision, we observe occasional QSPI read failures and flash communication instability.
During analysis we found:
1. QSPI signal overshoot
• QSPI_CLK and IO lines reach up to 4.7 V (measured on oscilloscope).
• This exceeds STM32 specification (VDD + 0.3 V).
According to AN5612 (ESD & internal clamp diode behavior):
If an I/O pin exceeds VDD + diode drop, the internal clamp diode conducts, which may cause:
Timing shift
Soft failures
Functional instability
Question:
→ Is overshoot of 4.7 V likely to disturb QSPI timing even if the current is low?
→ Is there a recommended clamp current limit for STM32H7 QSPI pins?
2. QSPI routing differences
Compared to V2 hardware (working), V3 has:
• All QSPI lines routed to 66.6 mm
• Serpentine added on CLK, CS, RESET
• Additional vias
• Closer traces to noisy areas (buzzer, LEDs, ESP32)
According to AN4661 – Section 8.4.3:
CLK must NOT be serpentine
CLK must be shortest path
Only IO0–IO3 should be length-matched
Route over continuous GND plane
Avoid vias and impedance discontinuities
Question:
→ Can serpentine on CLK + long trace length distort the signal enough to cause timing jitter or overshoot?
→ Is matching CS and RESET to 66 mm considered a design violation for QSPI?
3. Firmware behavior
After modifying UART-RTOS event handling, V3 behaves better, but V2 never needed firmware changes.
Question:
→ Does QSPI margin degradation due to hardware layout typically produce "borderline” behavior where firmware timing becomes more sensitive?
4. Request
Could ST please clarify:
Whether the 4.7 V overshoot is safe for STM32H755 QSPI pins
Whether V3 routing violates best-practice QSPI layout rules
Whether such routing can cause sporadic failures at 100 MHz
Any recommended steps (series resistors, termination, drive strength tuning)
I can share schematics and layout if needed.
Thank you for your guidance.
