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Problem with RTC when switching off (VDD) on H7

AScha.3
Principal III

Hi,

We have now a problem with some boards, H7A3ZI or H743ZI , when switching off :   RTC stops working !

RTC is powered on VBAT with a standard CR2032 and was working as it should on about 500 boards since more than a year. Now (some) batteries loosing voltage and we get errors, because RTC no more working.

This happend at first at about 2,7V (cell voltage), now even on new boards with 3,0V cells.

The problem starts at the moment of power off, when VDD falling (to 2V or so) , the internal switch going to use the VBAT as supply for RTC and backup ram. On affected boards is about 5 ms (!) long the LSE oscillation away, then starting (on VBAT supplied now) again - or no more, showing the error on next startup.

Is there anything we can do, to avoid this ? Or is there some "known problem" with the H7 series, when switching to VBAT ?   (In errata i found nothing about this problem.)

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1 ACCEPTED SOLUTION

Accepted Solutions

One Question please:

What about PDR_ON connection? connected to VDD or GND?

If PDR is not enabled (PDR_ON connected to GND), VBAT function is no more available.

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10 REPLIES 10
Peter BENSCH
ST Employee

It could be an unsuitable 2032, e.g. with a particularly high internal resistance. RM0433 also describes in the warning in section 6.4.4 that the power switch between VBAT and VDD remains switched on with a PDR, which can have such an effect if the internal resistance of the 2032 is high and causes some significant delay together with the sum of the buffer capacitors.

Please check the internal resistance of the 2032 of working and non-working boards.

Regards
/Peter

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Thx Peter, for quick response.

We have a 10uF cer.cap at VBAT ; and the bad behavior is same, when supplying VBAT from a lab supply :  at 3,0V all is fine, when going down to 2,7V "problem" arises.

Although it should work down to 1,2V (vbat) :

AScha3_0-1709039308621.png

 

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Peter BENSCH
ST Employee

The oscillation of the LSE that is missing for 5ms looks like a restart of the LSE, but I have not yet encountered this. Although the layout on the LSE usually plays a very important role, it shouldn't be relevant in this case. Let's see if I or other community members can think of anything else.

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Are you using LSI as source clock for RTC? I guess not.. but better to confirm.

SofLit_0-1709042447854.png

 

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LSE , only , is used for RTC/time clock.

+ Just changing a crystal - to check, whether crystal quality has any influence .

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SofLit
ST Employee

humm strange behavior .. 

I will try to reproduce it on NUCLEO-H743 board (STM32H743 rev V) and get back to you with my findings.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

One Question please:

What about PDR_ON connection? connected to VDD or GND?

If PDR is not enabled (PDR_ON connected to GND), VBAT function is no more available.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

OMG.

PDR_ON is open... clever , eh ?

I need a Whiskey now. 

from ds :

AScha3_0-1709053518045.png

This explains the curious behavior - right ?

Thanks alot , @SofLit  !

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Update...workmate tried it already , didnt change behaviour , he said.

I will try tomorrow myself.

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