Memory sharing between M7 and M4 - STM32H745

[Nsg1987]

Hello,

I am working on STM32H745 controller. I want to share a variable between M7 and M4.

Example: Variable named counter will be updated by M4 after some period and same has to be read by M7 for further processing.

Can anyone help me with suitable application note or any nucleo-h745 example code?

Regards,

Nikhil

[Sarra.S]

Hello @Nsg1987, 

You can use the STM32H7 dual-core inter-processor communication feature IPC to define a shared memory region that can be accessible by both cores.

Please check AN5617 and this video 

Hope that helps!

[Nsg1987]

Hello @Sarra.S 

Thanks for sharing. I downloaded the same code but found below errors.

../../Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/mdk-arm/errno.h:19:2: error: #error "Include metal/errno.h instead of metal/mdk-arm/errno.h"
19 | #error "Include metal/errno.h instead of metal/mdk-arm/errno.h"
| ^~~~~
make: *** [Core/Src/subdir.mk:31: Core/Src/sysmem.o] Error 1
make: *** Waiting for unfinished jobs....
In file included from ../Core/Src/syscalls.c:26:
../../Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/mdk-arm/errno.h:19:2: error: #error "Include metal/errno.h instead of metal/mdk-arm/errno.h"
19 | #error "Include metal/errno.h instead of metal/mdk-arm/errno.h"
| ^~~~~
make: *** [Core/Src/subdir.mk:31: Core/Src/syscalls.o] Error 1
"make -j20 all" terminated with exit code 2. Build might be incomplete.

could you please see and help me to resolve the above error.

Nikhil

[Piranha]

OpenAMP... :beaming_face_with_smiling_eyes: C'mon, just create a volatile variable/structure at a specific address in a shared memory and it's done! Though on the M7 side you have to configure or maintain the D-cache also. And for a more complex scenarios take a look at this:

https://github.com/MaJerle/stm32h7-dual-core-inter-cpu-async-communication

[Nsg1987]

Hello @Piranha 

with openAMP I sent data from M7 to M4 (HSEM1 and HSEM2 global interrupt) but found that controller remains busy doing it. Could you share any other way where data can be sent from one core to another core and controller also remains free to do other activities.

[Piranha]

My previous post literally shows such ways. Maybe try actually reading it...