Maximum TRACECLK frequency of STM32H725

[BGo]

Hello,

I have not found the maximum TRACECLK frequency of the STM32H725 in the documentation. It looks like it is generated by PLL1 with flexible division ratios and thus can attain values that are not realistic for I/Os (100 to 220 MHz for Speed 11 and 2.7 V ≤ VDD ≤ 3.6 V as per p.165 of DS13311).

Is the maximum TRACECLK set by the maximum I/O output frequency or is it restricted to another value?

Regards,
Bernd

[mƎALLEm]

Hello @BGo and welcome to the ST community,

You can reach 170MHz with the IO when HSLV is ON / Speed = 11.

DS13311 Rev 5 / Table 59:

" as per p.165 of DS13311" is for HSLV OFF

[BGo]

Hi @mƎALLEm,

thank you!

Is this also the maximum allowable frequency for TRACECLK, i.e., the limit is the maximum I/O output frequency?

Regards,
Bernd

[mƎALLEm · Accepted solution]

Hello,

The maximum TRACECLK frequency is not explicitly indicated in the documentation, according to this statement in the reference manual:

TRACECLK is derived either from the system clock (sys_ck) or from the PLL1 (pll1_r_ck).

So in conclusion you can use any of these clock sources by respecting the IO maximum frequency at the conditions provided in the datasheet.

Hope I answered your question.

[BGo]

Thank you!