Skip to main content
dave2012
dave2012
Associate III
December 27, 2019
Question

Known issues with D-cache and FMC on STM32F7

  • December 27, 2019
  • 7 replies
  • 6349 views

Hi,

I'm using a STM32F765 clocked at 216MHz and when D-Cache is enabled it badly affects reads from a device connected via the external FMC address/data bus (NE1, 16 bit data, 10 bit address). The following pictures show the problem (note ringing is caused by non-optimum scope lead grounding)

D-Cache On:

0690X00000Buz5hQAB.jpg

D-Cache off (expected result & same time base as above):

0690X00000Buz6zQAB.jpgD-Cache off (expected result, zoomed in)

0690X00000Buz7EQAR.jpg

I've checked the datasheets and errata but there is no mention of the issue I'm seeing. My multi-layer board is well decoupled, has ground & power planes and traces are short.

Has anyone come across this issue with D-Cache affecting FMC accesses ?

Thanks

Dave

This topic has been closed for replies.

7 replies

Tesla DeLorean
Tesla DeLorean
Guru
December 27, 2019

So what does "badly affects reads" actually mean?

Looks to be doing 16 operations for the cache-line.

Why not turn off caching for the FMC region if you don't want it buffered/cached?

Tips, Buy me a coffee, or three.. PayPal Venmo (See Profile) Up vote any posts that you find helpful, it shows what's working..
dave2012
dave2012Author
Associate III
December 27, 2019

Clive

Perhaps 'badly affects' should be re-worded as 'unexpected effect' i.e. I wasn't expecting this behaviour.

I had considered turning off data caching when accessing this device but changing the cache enable setting has a fair bit of overhead. Is there a way of statically excluding the FMC region as your question alludes to ?

Dave

Tesla DeLorean
Tesla DeLorean
Guru
December 27, 2019

You can config the MPU, likely several examples using a form similar to this

/** 
 * @brief Configure the MPU attributes as Normal Non Cacheable for SRAM1/2.
 * @note The Base Address is 0x20010000 since this memory interface is the AXI.
 * The Region Size is 512KB, it is related to SRAM1 and SRAM2 memory size.
 * @param None
 * @retval None
 */
static void MPU_Config(void)
{
 MPU_Region_InitTypeDef MPU_InitStruct;
 
 /* Disable the MPU */
 HAL_MPU_Disable();
 
 /* Configure the MPU as Normal Non Cacheable for the SRAM1 and SRAM2 */
 MPU_InitStruct.Enable = MPU_REGION_ENABLE;
 MPU_InitStruct.BaseAddress = 0x20020000; // <<<< Change to FMC base
 MPU_InitStruct.Size = MPU_REGION_SIZE_512KB;
 MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
 MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
 MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
 MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
 MPU_InitStruct.Number = MPU_REGION_NUMBER1;
 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
 MPU_InitStruct.SubRegionDisable = 0x00;
 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
 
 HAL_MPU_ConfigRegion(&MPU_InitStruct);
 
 /* Enable the MPU */
 HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}

Tips, Buy me a coffee, or three.. PayPal Venmo (See Profile) Up vote any posts that you find helpful, it shows what's working..
dave2012
dave2012Author
Associate III
December 27, 2019

Many thanks Clive - I had the MPU disabled so I'll have a play to see the effect of this.

Dave

Nick van IJzendoorn
Nick van IJzendoorn
Associate III
January 23, 2021

Although this post helped me there is an improvement to be made to the MPU configuration of Tesla which berendi did. The memory type has to be configured as Device or Strongly Ordered. (as berendi did, but I preferred the HAL implementation because it's better documented for the customer)

Please see the following post for more information on the TEX configuration and/or required memory barriers: https://community.st.com/s/question/0D50X00009hog4ISAQ/stm32f7h7-fmc-external-norflash-memory-why-it-works-only-by-use-dsb-command-for-cortexm7?t=1611421398835

Stan
Stan
Visitor II
November 24, 2021

Hello,

I am facing same problem, FMC performs 8 instead of 1 write operation.

I have remaped FMC to 0xC0000000, but without result. Theoretically 0xC0000000 region of memory is not cacheable, so problem should be solved. Maybe there is problem with something else?

MPU configured to disable caching (for 0x60000000 and 0xC0000000) also did not work. I have tried many MPU configurations with no result, is it possible that I have missed the correct one?

I have also tried to invalidate cache data before FMC write operation, but without results.

To clarify situation:

MCU I am using is STM32H743. Ethernet, sdmmc and many other interfaces are active, so maybe there is some hardware interference?

I have observed that when I create new project with FMC only, remaping FMC bank to 0xC0000000 solves the problem. Unfortunately project I am working on is huge and additionaly made by someone else soI am afraid that recreation may result in some failures that I will not be able to recognise.

waclawek.jan
waclawek.jan
Super User
November 24, 2021

> Theoretically 0xC0000000 region of memory is not cacheable

It's not cached by default, but that can be changed in MPU.

Maybe the huge project contains MPU configuration you don't know about. Try to read out the MPU or place data breakpoints (watchpoints) to its registers to capture any writes to it.

JW

Stan
Stan
Visitor II
November 25, 2021

Thank you for your answer.

I've checked MPU register and there are 3 protected regions but all of them are refering to D2 RAM region.

The problem starts to be really annoying becouse I haven't made any progress since monday.

Terms & ConditionsAccessibility statement