Inquiry regarding the internal behavior of the NRST pin on STM32H563ZIT6

[leejunggyun]

Hello,

I am currently reviewing a hardware design based on the STM32H563ZIT6 and have some questions regarding the internal and external behavior of the NRST pin.

My main question is how the NRST pin operates specifically during an NVIC_SystemReset.

Currently, we are using an external pull-up resistor (connected to 3.3V) on the NRST pin.

According to the Datasheet (DS) and Reference Manual (RM), I confirmed that the NRST pin has an internal weak pull-up (R_PU), which is typically 40 kΩ.

Although the Datasheet and Reference manual do not explicitly disclose the internal circuit diagram of the NRST pin used during NVIC_SystemReset, I found information in the community stating that NRST internally has an "Open-drain" structure.

link : https://community.st.com/t5/stm32-mcus/why-my-stm32-doesn-t-start/ta-p/49367

Therefore, I assume the circuit topology is as follows:

• R_pu: STM32 internal weak pull-up (typically 40 kΩ)
• R_nrst: The external pull-up resistor we attached (currently 10 kΩ)
• V_nrst: The voltage input to the STM32
• R_nmos: The channel resistance when the NMOS is turned ON
• V_{system_reset}: The system reset voltage to open the channel during NVIC_SystemReset

My understanding of the operation is as follows:

1. When an internal reset occurs: The internal logic turns the NMOS ON → NRST falls to LOW, triggering a reset.
   • Condition: It must be below V_IL. (We use V_DD = 3.3V, so V_IL should be around 0.99V).

When the NMOS turns ON, it will appear as a resistor due to its internal resistance (R_nmos).

During the reset drive, the voltage at the NRST pin will be divided as follows:

V_nrst = V_DD × (R_nmos / R_total + R_nmos)

The equivalent resistance of the parallel pull-up resistors is:

R_total = (R_pu × R_nrst) / (R_pu + R_nrst)

If R_nrst is much smaller than R_pu, R_total will effectively be seen as R_nrst (the external pull-up we attached).

If we consider a case where R_nmos is equal to R_total, then V_nrst would be 1.65V, which is far above the V_IL threshold.
Consequently, NVIC_SystemReset would not function correctly.

Here are my questions:

1. Is this circuit topology correct?
2. Is there a guaranteed specification for the sink capability (VOL vs IOL) of the NRST pin when it drives low during a SW reset?
3. Is there a minimum recommended value (or a prohibited range) for the external pull-up resistor on the NRST pin to ensure proper reset behavior?

I looked through the datasheet, but I could not find the VOL and IOL specifications for the NRST pin

Since we have already attached the external pull-up resistor to the circuit, I want to calculate accurately whether our design might have issues.
We attached a 10 kΩ resistor, and we confirmed that the reset works well during NVIC_SystemReset.
However, I am concerned whether the reset might fail during actual system operation, especially since the community mentions not to drive the voltage externally.

[Peter BENSCH]

This is still a common misconception, the origins of which date back to the last millennium when external pull-ups were connected to reset pins of ancient microcontrollers (the pensioners among us still remember: aaah, back then...). An external pull-up is NOT necessary, as you yourself have deduced from the internal pull-up. This renders any discussion about levels and potentially poor Rnmos obsolete.

Does it answer your question?

Regards
/Peter

[leejunggyun]

Hi @Peter BENSCH 

Thanks for the clarification. I agree an external pull-up is not required for a new design.

In our case, the boards are already manufactured with a 10 kΩ pull-up to 3.3 V on NRST.

I cannot easily remove them at this stage.

Could you please confirm one of the following:

Is 10 kΩ considered an acceptable external pull-up value for NRST on STM32H563?

If there is any official guidance, what is the minimum recommended (or prohibited) range for an external pull-up on NRST?
(We couldn’t find NRST VOL/IOL or sink capability specs in the datasheet.)

We have verified that NVIC_SystemReset() works with 10 kΩ, but we want to ensure there is no corner-case risk.

Regards,