The crypto chip ATSHA204A needs a >60us low pulse on the I2C SDA line to wakeup. After that pulse the SDA should be high for at least 2.5ms. How must the I2C be configured to create the described pulse? The attached pictures shows a transfer with address = 0x00 and the NACK/STOP at the end. The last pulse with NACK/STOP should be avoided and I don't know how to do that without bitbanging the SCL/SDA pins.
