How can I find the registers' addresses of STM32L053R8

[butterfly]

To Andrew, SofLi

Hy Andrew and SofLi. I well received your last informations posted this week-end. Therefore it was week-end.

I test a NUCLEO board without ST-link; my computer is a Mac-mini and the NUCLEO board offers capabilities to be separate in to part, the ST-link microcontroller and the targeted microcontroller, enabling to reduce power consumption on plant. Bootloader offer capability to read and write any address in address space; then I think the simply way to give you understable informations it's to give you an excell file with the list of my search. Hoping this is nice to you, I hope an answer.

Best regards.

Butterfly.

[Andrew Neil]

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@butterfly wrote:

I well received your last informations posted this week-end.

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Why not continue in that thread?

Please give a link so we can find what you're referring to.

I don't wish to open unknown XLSX files from the internet - sorry.

[SofLit]

Hello,

As I said in this thread https://community.st.com/t5/stm32-mcus-products/looking-for-registers-informations-to-configure-stm32l0-series/td-p/635100,

The base address of the peripherals are provided in the reference manual.

Then you compute each register absolute address based on its offset of its related peripheral.

Absolute register address = peripheral start address + register offset

Example:

FLASH_ACR address offset = 0x0000 0000

Flash registers base address 0X4002 2000

FLASH_ACR Absolute address = 0X4002 2000 + 0x0000 0000 = 0X4002 2000

[Andrew Neil]

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@SofLit wrote:

Hello,

As I said in this thread https://community.st.com/t5/stm32-mcus-products/looking-for-registers-informations-to-configure-stm32l0-series/td-p/635100,

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The forum has broken that link:

(probably due to the trailing comma?)

Try:

https://community.st.com/t5/stm32-mcus-products/looking-for-registers-informations-to-configure-stm32l0-series/td-p/635100

[Andrew Neil]

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@SofLit wrote:

Then you compute each register absolute address based on its offset of its related peripheral.

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@butterfly and, as already noted, ST provide a header file which has already done all those computations - and more - for you.

No need to re-invent the wheel!

[butterfly]

Hy thanks to don't need to re-invent the wheel. In my file each register named is at an absolute address with a 0 offset. That mean for each peripheral there are different base addresses with offset for each following registers.

If you have an include file which can be part of standard delivery may I find it on a server dedicated to st-community or could you send me a copy?

Best regards.

Alain LE BLOA.

[Andrew Neil]

See your previous thread:

https://community.st.com/t5/stm32-mcus-products/looking-for-registers-informations-to-configure-stm32l0-series/m-p/635134/highlight/true#M234316

Again, what was the point in starting a new thread? Now you're just confusing the issue by having the discussion spread across two threads!

[SofLit · Accepted solution]

Found in stm32l053xx.h (located under Drivers\CMSIS\Device\ST\STM32L0xx\Include in STM32CubeL0 package) in attachment:

#define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */

/*!< Peripheral memory map */
#define APBPERIPH_BASE        PERIPH_BASE
#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)

#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
#define LCD_BASE              (APBPERIPH_BASE + 0x00002400UL)
#define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
#define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00UL)
#define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
#define DAC_BASE              (APBPERIPH_BASE + 0x00007400UL)
#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)

#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
#define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00UL)
#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
#define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)

#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)


#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
#define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
#define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
#define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000UL)
#define RNG_BASE              (AHBPERIPH_BASE + 0x00005000UL)

#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00UL)
#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)

Based on that, you can add the registers' offsets.

[waclawek.jan]

https://github.com/STMicroelectronics/STM32CubeL0/tree/master/Drivers/CMSIS/Device/ST  click on STM32L0xx @ b3b1d7b -> Include -> https://github.com/STMicroelectronics/cmsis_device_l0/tree/b3b1d7b134f5408c3e75363754d44a6aa11b1db1/Include

You are supposed to #include "stm32l0xx.h" while having defined STM32L053xx symbol (i.e. either #define STM32L053xx before the #include; or better, -DSTM32L053xx in command-line). stm32l0xx.h will include also relevant generic-ARM CMSIS headers from https://github.com/STMicroelectronics/STM32CubeL0/tree/master/Drivers/CMSIS/Core/Include

JW

[Andrew Neil]

For the NUCLEO L053R8 board, go to the Product Page, and look under 'Tools & Software':

https://www.st.com/en/evaluation-tools/nucleo-l053r8.html#tools-software

Look at the 'MCU & MPU Embedded Software' section - the STM32CubeL0 pack will have what you need:

https://www.st.com/en/embedded-software/stm32cubel0.html