2017-08-05 01:25 AM
Can not find any related flag in RM0090 at lest. Strongly need to receive frames with lengths down to 12 byte totally (having only SA DA at most )
2017-08-05 05:38 AM
It uses third-party IP, so the docs aren't likely to be super detailed.
I would expect that it would receive them, not sure if there is a specific flag identifying them, other hardware I've used for this just passes you a length of what was received, even if that was less than 64 bytes. Think you'll just need to experiment.
2017-08-05 07:40 AM
Can not find any related flag in RM0090
ETH_DMAOMR.FUGF?
JW
2017-08-05 09:43 AM
thank you for quick reply
Document says it can receive short frames, but very short frames are not traced in program (oscilloscope clearly detects data from phy (dp83848)). Smallest receive threshold option(for cut-through mode) is 32 byte - much more than I want. Though it promisses to immideately pass runt frames that are shorter than threshold. I guessthe issue is much earlier than DL level; Any way I have to double check all settings. I should try MII mode too. If it doesnt work, at least I can modify CRS (carrier sense) signal with additional HW(to receive additional zeroes if it passes wrong CRC) or even try receive packet with DMA into memory from PHY;
I need to develop some custom highly synched protocol, where full packet is too long. Hope cheaper cortex will save production costs (very unwilling to dig into fpga). The data rate and the degree the internat ETH/MAC is tweakable are very good.
2017-08-05 09:52 AM
Yeah, tried that; it promissed all the good but still cant receive that packet (from SFD it is only 12bytes + 4 bytes of 802.3 standard FCS ). Receive own mode gets such packet well.
I hope it is some of my mistake (I use RMII mode on custom board with other settings that are subject to re-check)
2017-08-05 10:00 AM
Does ETH_DMAMFBOCR change?
JW
2017-08-05 10:15 AM
Appears to be zero..
CRS signal seems to be fuzzy, but it clearly detects regular packets from laptop if I inject them..
2017-08-05 10:26 AM
Now I see the text that the counter has to be increased
due to Rx FIFO overflow conditions and runt frames (good frames of less than 64 bytes)
but still figuring out whats wrong. You note is an indication where to search next.
Something either tricky or obvious (any way the most of work has to be mine)
2017-08-19 10:00 AM
My problem was in disabled autonegotiation though I chose correct mode (it seems like autonegotiation helps to synchronize clock(s) in RMII mode. there was a moment in which it had received distorted data.)